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/Zephyr-Core-3.5.0/drivers/cache/
Dcache_aspeed.c53 uint32_t start_bit, end_bit, max_bit; in aspeed_cache_init() local
60 start_bit = MIN(max_bit, CACHED_SRAM_ADDR >> CACHE_AREA_SIZE_LOG2); in aspeed_cache_init()
62 syscon_write_reg(dev, CACHE_AREA_CTRL_REG, GENMASK(end_bit, start_bit)); in aspeed_cache_init()