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Searched refs:region_size (Results 1 – 11 of 11) sorted by relevance

/Zephyr-Core-3.5.0/soc/arm/renesas_smartbond/da1469x/
Dsoc.c45 uint32_t region_size; in z_renesas_configure_cache() local
54 region_size = (uint32_t)&__rom_region_end - cache_start; in z_renesas_configure_cache()
65 if (region_size > MB(16)) { in z_renesas_configure_cache()
67 } else if (region_size > MB(8)) { in z_renesas_configure_cache()
69 } else if (region_size > MB(4)) { in z_renesas_configure_cache()
71 } else if (region_size > MB(2)) { in z_renesas_configure_cache()
73 } else if (region_size > MB(1)) { in z_renesas_configure_cache()
75 } else if (region_size > KB(512)) { in z_renesas_configure_cache()
77 } else if (region_size > KB(256)) { in z_renesas_configure_cache()
/Zephyr-Core-3.5.0/tests/application_development/code_relocation/
Dlinker_xtensa_qemu_sram2.ld26 #define MPU_ALIGN(region_size) \ argument
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/andes_v5/ae350/
Dlinker.ld64 #define MPU_ALIGN(region_size) \ argument
66 . = ALIGN( 1 << LOG2CEIL(region_size))
68 #define MPU_ALIGN(region_size) \ argument
73 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
206 #define MPU_ALIGN(region_size) \ argument
208 . = ALIGN( 1 << LOG2CEIL(region_size))
/Zephyr-Core-3.5.0/include/zephyr/arch/arc/v2/
Dlinker.ld42 #define MPU_ALIGN(region_size) \ argument
44 . = ALIGN( 1 << LOG2CEIL(region_size))
46 #define MPU_ALIGN(region_size) \ argument
51 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/common/
Dlinker.ld63 #define MPU_ALIGN(region_size) \ argument
65 . = ALIGN( 1 << LOG2CEIL(region_size))
67 #define MPU_ALIGN(region_size) \ argument
72 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/
Dlinker.ld56 #define MPU_ALIGN(region_size) \ argument
58 . = ALIGN( 1 << LOG2CEIL(region_size))
60 #define MPU_ALIGN(region_size) \ argument
65 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_npcx_fiu_nor.c64 size_t region_size) in is_within_region() argument
67 (addr < (region_start + region_size)) && in is_within_region()
68 ((addr + size) <= (region_start + region_size))); in is_within_region()
/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_a_r/scripts/
Dlinker.ld68 #define MPU_ALIGN(region_size) \ argument
70 . = ALIGN(1 << LOG2CEIL(region_size))
72 #define MPU_ALIGN(region_size) \ argument
/Zephyr-Core-3.5.0/samples/boards/intel_adsp/code_relocation/
Dlinker_xtensa_intel_adsp_cavs.ld49 #define MPU_ALIGN(region_size) \ argument
/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_m/scripts/
Dlinker.ld70 #define MPU_ALIGN(region_size) \ argument
72 . = ALIGN( 1 << LOG2CEIL(region_size))
74 #define MPU_ALIGN(region_size) \ argument
/Zephyr-Core-3.5.0/arch/x86/
Dgen_mmu.py504 region_size = region_end - region_start
511 self.map(region_start_phys, region_start, region_size, flags, level)