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Searched refs:port1 (Results 1 – 8 of 8) sorted by relevance

/Zephyr-Core-3.5.0/samples/subsys/usb_c/source/src/
Dmain.c18 #define PORT1_NODE DT_NODELABEL(port1)
19 #define PORT1_POWER_ROLE DT_ENUM_IDX(DT_NODELABEL(port1), power_role)
34 uint32_t src_caps[DT_PROP_LEN(DT_NODELABEL(port1), source_pdos)];
52 .rp = DT_ENUM_IDX(DT_NODELABEL(port1), typec_power_opmode),
53 .src_caps = {DT_FOREACH_PROP_ELEM(DT_NODELABEL(port1), source_pdos, SOURCE_PDO)},
54 .src_cap_cnt = DT_PROP_LEN(DT_NODELABEL(port1), source_pdos),
/Zephyr-Core-3.5.0/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.c105 uint16_t port1, port2; in display_chars() local
114 port1 = ((chars[3] & 0x7f) << 7) | (chars[2] & 0x7f); in display_chars()
118 r = gpio_port_set_masked(expander1, 0x3fff, port1 ^ 0x3fff); in display_chars()
/Zephyr-Core-3.5.0/samples/subsys/usb_c/sink/src/
Dmain.c16 #define PORT1_NODE DT_NODELABEL(port1)
17 #define PORT1_POWER_ROLE DT_ENUM_IDX(DT_NODELABEL(port1), power_role)
31 uint32_t snk_caps[DT_PROP_LEN(DT_NODELABEL(port1), sink_pdos)];
41 .snk_caps = {DT_FOREACH_PROP_ELEM(DT_NODELABEL(port1), sink_pdos, SINK_PDO)},
42 .snk_cap_cnt = DT_PROP_LEN(DT_NODELABEL(port1), sink_pdos),
/Zephyr-Core-3.5.0/samples/subsys/usb_c/sink/boards/
Dstm32g081b_eval.overlay25 port1: usbc-port@1 {
Db_g474e_dpow1.overlay24 port1: usbc-port@1 {
/Zephyr-Core-3.5.0/tests/drivers/build_all/ethernet/
Dapp.overlay73 port1 {
98 port1 {
/Zephyr-Core-3.5.0/boards/arm/stm32g081b_eval/doc/
Dindex.rst74 - Mux for USB3.1 Gen1 / DisplayPort input and Type-C port1 output
76 - VCONN on Type-C port1
77 - USB PD on Type-C port1
79 - Type-C port1 DRP (dual-role port)
/Zephyr-Core-3.5.0/samples/subsys/usb_c/source/boards/
Dstm32g081b_eval.overlay65 port1: usbc-port@1 {