1 /*
2  * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT ite_it8xxx2_espi
8 
9 #include <assert.h>
10 #include <zephyr/drivers/espi.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
13 #include <zephyr/kernel.h>
14 #include <soc.h>
15 #include <soc_dt.h>
16 #include "soc_espi.h"
17 #include "espi_utils.h"
18 
19 #include <zephyr/logging/log.h>
20 #include <zephyr/irq.h>
21 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
22 
23 #define ESPI_IT8XXX2_GET_GCTRL_BASE \
24 	((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
25 
26 #define IT8XXX2_ESPI_IRQ     DT_INST_IRQ_BY_IDX(0, 0, irq)
27 #define IT8XXX2_ESPI_VW_IRQ  DT_INST_IRQ_BY_IDX(0, 1, irq)
28 #define IT8XXX2_KBC_IBF_IRQ  DT_INST_IRQ_BY_IDX(0, 2, irq)
29 #define IT8XXX2_KBC_OBE_IRQ  DT_INST_IRQ_BY_IDX(0, 3, irq)
30 #define IT8XXX2_PMC1_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 4, irq)
31 #define IT8XXX2_PORT_80_IRQ  DT_INST_IRQ_BY_IDX(0, 5, irq)
32 #define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq)
33 #define IT8XXX2_TRANS_IRQ    DT_INST_IRQ_BY_IDX(0, 7, irq)
34 
35 /* General Capabilities and Configuration 1 */
36 #define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0)
37 #define IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_20 0
38 #define IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_25 1
39 #define IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_33 2
40 #define IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_50 3
41 #define IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_66 4
42 
43 #define IT8XXX2_ESPI_PC_READY_MASK  BIT(1)
44 #define IT8XXX2_ESPI_VW_READY_MASK  BIT(1)
45 #define IT8XXX2_ESPI_OOB_READY_MASK BIT(1)
46 #define IT8XXX2_ESPI_FC_READY_MASK  BIT(1)
47 
48 #define IT8XXX2_ESPI_INTERRUPT_ENABLE          BIT(7)
49 #define IT8XXX2_ESPI_TO_WUC_ENABLE             BIT(4)
50 #define IT8XXX2_ESPI_VW_INTERRUPT_ENABLE       BIT(7)
51 #define IT8XXX2_ESPI_INTERRUPT_PUT_PC          BIT(7)
52 
53 /*
54  * VWCTRL2 register:
55  * bit4 = 1b: Refers to ESPI_RESET# for PLTRST#.
56  */
57 #define IT8XXX2_ESPI_VW_RESET_PLTRST           BIT(4)
58 
59 #define IT8XXX2_ESPI_UPSTREAM_ENABLE           BIT(7)
60 #define IT8XXX2_ESPI_UPSTREAM_GO               BIT(6)
61 #define IT8XXX2_ESPI_UPSTREAM_INTERRUPT_ENABLE BIT(5)
62 #define IT8XXX2_ESPI_UPSTREAM_CHANNEL_DISABLE  BIT(2)
63 #define IT8XXX2_ESPI_UPSTREAM_DONE             BIT(1)
64 #define IT8XXX2_ESPI_UPSTREAM_BUSY             BIT(0)
65 
66 #define IT8XXX2_ESPI_CYCLE_TYPE_OOB            0x07
67 
68 #define IT8XXX2_ESPI_PUT_OOB_STATUS            BIT(7)
69 #define IT8XXX2_ESPI_PUT_OOB_INTERRUPT_ENABLE  BIT(7)
70 #define IT8XXX2_ESPI_PUT_OOB_LEN_MASK          GENMASK(6, 0)
71 
72 #define IT8XXX2_ESPI_INPUT_PAD_GATING          BIT(6)
73 
74 #define IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE    64
75 #define IT8XXX2_ESPI_PUT_FLASH_TAG_MASK        GENMASK(7, 4)
76 #define IT8XXX2_ESPI_PUT_FLASH_LEN_MASK        GENMASK(6, 0)
77 
78 struct espi_it8xxx2_wuc {
79 	/* WUC control device structure */
80 	const struct device *wucs;
81 	/* WUC pin mask */
82 	uint8_t mask;
83 };
84 
85 struct espi_it8xxx2_config {
86 	uintptr_t base_espi_slave;
87 	uintptr_t base_espi_vw;
88 	uintptr_t base_espi_queue1;
89 	uintptr_t base_espi_queue0;
90 	uintptr_t base_ec2i;
91 	uintptr_t base_kbc;
92 	uintptr_t base_pmc;
93 	uintptr_t base_smfi;
94 	const struct espi_it8xxx2_wuc wuc;
95 };
96 
97 struct espi_it8xxx2_data {
98 	sys_slist_t callbacks;
99 #ifdef CONFIG_ESPI_OOB_CHANNEL
100 	struct k_sem oob_upstream_go;
101 #endif
102 #ifdef CONFIG_ESPI_FLASH_CHANNEL
103 	struct k_sem flash_upstream_go;
104 	uint8_t put_flash_cycle_type;
105 	uint8_t put_flash_tag;
106 	uint8_t put_flash_len;
107 	uint8_t flash_buf[IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE];
108 #endif
109 };
110 
111 struct vw_channel_t {
112 	uint8_t  vw_index;      /* VW index of signal */
113 	uint8_t  level_mask;    /* level bit of signal */
114 	uint8_t  valid_mask;    /* valid bit of signal */
115 };
116 
117 struct vwidx_isr_t {
118 	void (*vwidx_isr)(const struct device *dev, uint8_t update_flag);
119 	uint8_t vw_index;
120 };
121 
122 enum espi_ch_enable_isr_type {
123 	DEASSERTED_FLAG = 0,
124 	ASSERTED_FLAG = 1,
125 };
126 
127 struct espi_isr_t {
128 	void (*espi_isr)(const struct device *dev, bool enable);
129 	enum espi_ch_enable_isr_type isr_type;
130 };
131 
132 struct espi_vw_signal_t {
133 	enum espi_vwire_signal signal;
134 	void (*vw_signal_isr)(const struct device *dev);
135 };
136 
137 /* EC2I bridge and PNPCFG devices */
138 static const struct ec2i_t kbc_settings[] = {
139 	/* Select logical device 06h(keyboard) */
140 	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
141 	/* Set IRQ=01h for logical device */
142 	{HOST_INDEX_IRQNUMX, 0x01},
143 	/* Configure IRQTP for KBC. */
144 	/*
145 	 * Interrupt request type select (IRQTP) for KBC.
146 	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
147 	 *        1: IRQ request is inverted before being applied to SERIRQ
148 	 * bit 0, 0: Edge triggered mode
149 	 *        1: Level triggered mode
150 	 *
151 	 * This interrupt configuration should the same on both host and EC side
152 	 */
153 	{HOST_INDEX_IRQTP, 0x02},
154 	/* Enable logical device */
155 	{HOST_INDEX_LDA, 0x01},
156 
157 #ifdef CONFIG_ESPI_IT8XXX2_PNPCFG_DEVICE_KBC_MOUSE
158 	/* Select logical device 05h(mouse) */
159 	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
160 	/* Set IRQ=0Ch for logical device */
161 	{HOST_INDEX_IRQNUMX, 0x0C},
162 	/* Enable logical device */
163 	{HOST_INDEX_LDA, 0x01},
164 #endif
165 };
166 
167 static const struct ec2i_t pmc1_settings[] = {
168 	/* Select logical device 11h(PM1 ACPI) */
169 	{HOST_INDEX_LDN, LDN_PMC1},
170 	/* Set IRQ=00h for logical device */
171 	{HOST_INDEX_IRQNUMX, 0x00},
172 	/* Enable logical device */
173 	{HOST_INDEX_LDA, 0x01},
174 };
175 
176 #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
177 #define IT8XXX2_ESPI_HC_DATA_PORT_MSB \
178 	((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff)
179 #define IT8XXX2_ESPI_HC_DATA_PORT_LSB \
180 	(CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM & 0xff)
181 #define IT8XXX2_ESPI_HC_CMD_PORT_MSB \
182 	(((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) >> 8) & 0xff)
183 #define IT8XXX2_ESPI_HC_CMD_PORT_LSB \
184 	((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) & 0xff)
185 static const struct ec2i_t pmc2_settings[] = {
186 	/* Select logical device 12h(PM2 host command) */
187 	{HOST_INDEX_LDN, LDN_PMC2},
188 	/* I/O Port Base Address (data/command ports) */
189 	{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HC_DATA_PORT_MSB},
190 	{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HC_DATA_PORT_LSB},
191 	{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HC_CMD_PORT_MSB},
192 	{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HC_CMD_PORT_LSB},
193 	/* Set IRQ=00h for logical device */
194 	{HOST_INDEX_IRQNUMX, 0x00},
195 	/* Enable logical device */
196 	{HOST_INDEX_LDA, 0x01},
197 };
198 #endif
199 
200 #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
201 	defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
202 /*
203  * Host to RAM (H2RAM) memory mapping.
204  * This feature allows host access EC's memory directly by eSPI I/O cycles.
205  * Mapping range is 4K bytes and base address is adjustable.
206  * Eg. the I/O cycle 800h~8ffh from host can be mapped to x800h~x8ffh.
207  * Linker script will make the pool 4K aligned.
208  */
209 #define IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX 0x1000
210 #define IT8XXX2_ESPI_H2RAM_OFFSET_MASK   GENMASK(5, 0)
211 
212 #if defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
213 #define H2RAM_ACPI_SHM_MAX ((CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) + \
214 			(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM))
215 #if (H2RAM_ACPI_SHM_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX)
216 #error "ACPI shared memory region out of h2ram"
217 #endif
218 #endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
219 
220 #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD)
221 #define H2RAM_EC_HOST_CMD_MAX ((CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE) + \
222 			(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
223 #if (H2RAM_EC_HOST_CMD_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX)
224 #error "EC host command parameters out of h2ram"
225 #endif
226 #endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD */
227 
228 #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) && \
229 	defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
230 #if (MIN(H2RAM_ACPI_SHM_MAX, H2RAM_EC_HOST_CMD_MAX) > \
231 	MAX(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM, \
232 		CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
233 #error "ACPI and HC sections of h2ram overlap"
234 #endif
235 #endif
236 
237 static uint8_t h2ram_pool[MAX(H2RAM_ACPI_SHM_MAX, H2RAM_EC_HOST_CMD_MAX)]
238 					__attribute__((section(".h2ram_pool")));
239 
240 #define H2RAM_WINDOW_SIZE(ram_size) ((find_msb_set((ram_size) / 16) - 1) & 0x7)
241 
242 static const struct ec2i_t smfi_settings[] = {
243 	/* Select logical device 0Fh(SMFI) */
244 	{HOST_INDEX_LDN, LDN_SMFI},
245 	/* Internal RAM base address on eSPI I/O space */
246 	{HOST_INDEX_DSLDC6, 0x00},
247 	/* Enable H2RAM eSPI I/O cycle */
248 	{HOST_INDEX_DSLDC7, 0x01},
249 	/* Enable logical device */
250 	{HOST_INDEX_LDA, 0x01},
251 };
252 
smfi_it8xxx2_init(const struct device * dev)253 static void smfi_it8xxx2_init(const struct device *dev)
254 {
255 	const struct espi_it8xxx2_config *const config = dev->config;
256 	struct smfi_it8xxx2_regs *const smfi_reg =
257 		(struct smfi_it8xxx2_regs *)config->base_smfi;
258 	struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
259 	uint8_t h2ram_offset;
260 
261 	/* Set the host to RAM cycle address offset */
262 	h2ram_offset = ((uint32_t)h2ram_pool & 0xffff) /
263 				IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX;
264 	gctrl->GCTRL_H2ROFSR =
265 		(gctrl->GCTRL_H2ROFSR & ~IT8XXX2_ESPI_H2RAM_OFFSET_MASK) |
266 		h2ram_offset;
267 
268 #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
269 	memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM], 0,
270 			CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
271 	/* Set host RAM window 0 base address */
272 	smfi_reg->SMFI_HRAMW0BA =
273 		(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM >> 4) & 0xff;
274 	/* Set host RAM window 0 size. (allow R/W) */
275 	smfi_reg->SMFI_HRAMW0AAS =
276 		H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
277 	/* Enable window 0, H2RAM through IO cycle */
278 	smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW0E);
279 #endif
280 
281 #ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
282 	memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM], 0,
283 			CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE);
284 	/* Set host RAM window 1 base address */
285 	smfi_reg->SMFI_HRAMW1BA =
286 		(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM >> 4) & 0xff;
287 	/* Set host RAM window 1 size. (read-only) */
288 	smfi_reg->SMFI_HRAMW1AAS =
289 		H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) |
290 		SMFI_HRAMWXWPE_ALL;
291 	/* Enable window 1, H2RAM through IO cycle */
292 	smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW1E);
293 #endif
294 }
295 #endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD ||
296 	* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
297 	*/
298 
ec2i_it8xxx2_wait_status_cleared(const struct device * dev,uint8_t mask)299 static void ec2i_it8xxx2_wait_status_cleared(const struct device *dev,
300 						uint8_t mask)
301 {
302 	const struct espi_it8xxx2_config *const config = dev->config;
303 	struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i;
304 
305 	while (ec2i->IBCTL & mask) {
306 		;
307 	}
308 }
309 
ec2i_it8xxx2_write_pnpcfg(const struct device * dev,enum ec2i_access sel,uint8_t data)310 static void ec2i_it8xxx2_write_pnpcfg(const struct device *dev,
311 					enum ec2i_access sel, uint8_t data)
312 {
313 	const struct espi_it8xxx2_config *const config = dev->config;
314 	struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i;
315 
316 	/* bit0: EC to I-Bus access enabled. */
317 	ec2i->IBCTL |= EC2I_IBCTL_CSAE;
318 	/*
319 	 * Wait that both CRIB and CWIB bits in IBCTL register
320 	 * are cleared.
321 	 */
322 	ec2i_it8xxx2_wait_status_cleared(dev, EC2I_IBCTL_CRWIB);
323 	/* Enable EC access to the PNPCFG registers */
324 	ec2i->IBMAE |= EC2I_IBMAE_CFGAE;
325 	/* Set indirect host I/O offset. */
326 	ec2i->IHIOA = sel;
327 	/* Write the data to IHD register */
328 	ec2i->IHD = data;
329 	/* Wait the CWIB bit in IBCTL cleared. */
330 	ec2i_it8xxx2_wait_status_cleared(dev, EC2I_IBCTL_CWIB);
331 	/* Disable EC access to the PNPCFG registers. */
332 	ec2i->IBMAE &= ~EC2I_IBMAE_CFGAE;
333 	/* Disable EC to I-Bus access. */
334 	ec2i->IBCTL &= ~EC2I_IBCTL_CSAE;
335 }
336 
ec2i_it8xxx2_write(const struct device * dev,enum host_pnpcfg_index index,uint8_t data)337 static void ec2i_it8xxx2_write(const struct device *dev,
338 				enum host_pnpcfg_index index, uint8_t data)
339 {
340 	/* Set index */
341 	ec2i_it8xxx2_write_pnpcfg(dev, EC2I_ACCESS_INDEX, index);
342 	/* Set data */
343 	ec2i_it8xxx2_write_pnpcfg(dev, EC2I_ACCESS_DATA, data);
344 }
345 
pnpcfg_it8xxx2_configure(const struct device * dev,const struct ec2i_t * settings,size_t entries)346 static void pnpcfg_it8xxx2_configure(const struct device *dev,
347 					const struct ec2i_t *settings,
348 					size_t entries)
349 {
350 	for (size_t i = 0; i < entries; i++) {
351 		ec2i_it8xxx2_write(dev, settings[i].index_port,
352 					settings[i].data_port);
353 	}
354 }
355 
356 #define PNPCFG(_s)						\
357 	pnpcfg_it8xxx2_configure(dev, _s##_settings, ARRAY_SIZE(_s##_settings))
358 
pnpcfg_it8xxx2_init(const struct device * dev)359 static void pnpcfg_it8xxx2_init(const struct device *dev)
360 {
361 	const struct espi_it8xxx2_config *const config = dev->config;
362 	struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i;
363 	struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
364 
365 	/* The register pair to access PNPCFG is 004Eh and 004Fh */
366 	gctrl->GCTRL_BADRSEL = 0x1;
367 	/* Host access is disabled */
368 	ec2i->LSIOHA |= 0x3;
369 	/* configure pnpcfg devices */
370 	if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_8042_KBC)) {
371 		PNPCFG(kbc);
372 	}
373 	if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_HOST_IO)) {
374 		PNPCFG(pmc1);
375 	}
376 #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
377 	PNPCFG(pmc2);
378 #endif
379 #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
380 	defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
381 	PNPCFG(smfi);
382 #endif
383 }
384 
385 /* KBC (port 60h/64h) */
386 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
kbc_it8xxx2_ibf_isr(const struct device * dev)387 static void kbc_it8xxx2_ibf_isr(const struct device *dev)
388 {
389 	const struct espi_it8xxx2_config *const config = dev->config;
390 	struct espi_it8xxx2_data *const data = dev->data;
391 	struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc;
392 	struct espi_event evt = {
393 		ESPI_BUS_PERIPHERAL_NOTIFICATION,
394 		ESPI_PERIPHERAL_8042_KBC,
395 		ESPI_PERIPHERAL_NODATA
396 	};
397 	struct espi_evt_data_kbc *kbc_evt =
398 			(struct espi_evt_data_kbc *)&evt.evt_data;
399 
400 	/* KBC Input Buffer Full event */
401 	kbc_evt->evt = HOST_KBC_EVT_IBF;
402 	/*
403 	 * Indicates if the host sent a command or data.
404 	 * 0 = data
405 	 * 1 = Command.
406 	 */
407 	kbc_evt->type = !!(kbc_reg->KBHISR & KBC_KBHISR_A2_ADDR);
408 	/* The data in KBC Input Buffer */
409 	kbc_evt->data = kbc_reg->KBHIDIR;
410 
411 	espi_send_callbacks(&data->callbacks, dev, evt);
412 }
413 
kbc_it8xxx2_obe_isr(const struct device * dev)414 static void kbc_it8xxx2_obe_isr(const struct device *dev)
415 {
416 	const struct espi_it8xxx2_config *const config = dev->config;
417 	struct espi_it8xxx2_data *const data = dev->data;
418 	struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc;
419 	struct espi_event evt = {
420 		ESPI_BUS_PERIPHERAL_NOTIFICATION,
421 		ESPI_PERIPHERAL_8042_KBC,
422 		ESPI_PERIPHERAL_NODATA
423 	};
424 	struct espi_evt_data_kbc *kbc_evt =
425 				(struct espi_evt_data_kbc *)&evt.evt_data;
426 
427 	/* Disable KBC OBE interrupt first */
428 	kbc_reg->KBHICR &= ~KBC_KBHICR_OBECIE;
429 
430 	/* Notify application that host already read out data. */
431 	kbc_evt->evt = HOST_KBC_EVT_OBE;
432 	kbc_evt->data = 0;
433 	kbc_evt->type = 0;
434 	espi_send_callbacks(&data->callbacks, dev, evt);
435 }
436 
kbc_it8xxx2_init(const struct device * dev)437 static void kbc_it8xxx2_init(const struct device *dev)
438 {
439 	const struct espi_it8xxx2_config *const config = dev->config;
440 	struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc;
441 
442 	/* Disable KBC serirq IRQ */
443 	kbc_reg->KBIRQR = 0;
444 
445 	/*
446 	 * bit3: Input Buffer Full CPU Interrupt Enable.
447 	 * bit1: Enable the interrupt to mouse driver in the host processor via
448 	 *       SERIRQ when the output buffer is full.
449 	 * bit0: Enable the interrupt to keyboard driver in the host processor
450 	 *       via SERIRQ when the output buffer is full
451 	 */
452 	kbc_reg->KBHICR |=
453 		(KBC_KBHICR_IBFCIE | KBC_KBHICR_OBFKIE | KBC_KBHICR_OBFMIE);
454 
455 	/* Input Buffer Full CPU Interrupt Enable. */
456 	IRQ_CONNECT(IT8XXX2_KBC_IBF_IRQ, 0, kbc_it8xxx2_ibf_isr,
457 			DEVICE_DT_INST_GET(0), 0);
458 	irq_enable(IT8XXX2_KBC_IBF_IRQ);
459 
460 	/* Output Buffer Empty CPU Interrupt Enable */
461 	IRQ_CONNECT(IT8XXX2_KBC_OBE_IRQ, 0, kbc_it8xxx2_obe_isr,
462 			DEVICE_DT_INST_GET(0), 0);
463 	irq_enable(IT8XXX2_KBC_OBE_IRQ);
464 }
465 #endif
466 
467 /* PMC 1 (APCI port 62h/66h) */
468 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
pmc1_it8xxx2_ibf_isr(const struct device * dev)469 static void pmc1_it8xxx2_ibf_isr(const struct device *dev)
470 {
471 	const struct espi_it8xxx2_config *const config = dev->config;
472 	struct espi_it8xxx2_data *const data = dev->data;
473 	struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
474 	struct espi_event evt = {
475 		ESPI_BUS_PERIPHERAL_NOTIFICATION,
476 		ESPI_PERIPHERAL_HOST_IO,
477 		ESPI_PERIPHERAL_NODATA
478 	};
479 	struct espi_evt_data_acpi *acpi_evt =
480 				(struct espi_evt_data_acpi *)&evt.evt_data;
481 
482 	/*
483 	 * Indicates if the host sent a command or data.
484 	 * 0 = data
485 	 * 1 = Command.
486 	 */
487 	acpi_evt->type = !!(pmc_reg->PM1STS & PMC_PM1STS_A2_ADDR);
488 	/* Set processing flag before reading command byte */
489 	pmc_reg->PM1STS |= PMC_PM1STS_GPF;
490 	acpi_evt->data = pmc_reg->PM1DI;
491 
492 	espi_send_callbacks(&data->callbacks, dev, evt);
493 }
494 
pmc1_it8xxx2_init(const struct device * dev)495 static void pmc1_it8xxx2_init(const struct device *dev)
496 {
497 	const struct espi_it8xxx2_config *const config = dev->config;
498 	struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
499 
500 	/* Enable pmc1 input buffer full interrupt */
501 	pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE;
502 	IRQ_CONNECT(IT8XXX2_PMC1_IBF_IRQ, 0, pmc1_it8xxx2_ibf_isr,
503 			DEVICE_DT_INST_GET(0), 0);
504 	irq_enable(IT8XXX2_PMC1_IBF_IRQ);
505 }
506 #endif
507 
508 /* Port 80 */
509 #ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
port80_it8xxx2_isr(const struct device * dev)510 static void port80_it8xxx2_isr(const struct device *dev)
511 {
512 	struct espi_it8xxx2_data *const data = dev->data;
513 	struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
514 	struct espi_event evt = {
515 		ESPI_BUS_PERIPHERAL_NOTIFICATION,
516 		(ESPI_PERIPHERAL_INDEX_0 << 16) | ESPI_PERIPHERAL_DEBUG_PORT80,
517 		ESPI_PERIPHERAL_NODATA
518 	};
519 
520 	evt.evt_data = gctrl->GCTRL_P80HDR;
521 	/* Write 1 to clear this bit */
522 	gctrl->GCTRL_P80H81HSR |= BIT(0);
523 
524 	espi_send_callbacks(&data->callbacks, dev, evt);
525 }
526 
port80_it8xxx2_init(const struct device * dev)527 static void port80_it8xxx2_init(const struct device *dev)
528 {
529 	ARG_UNUSED(dev);
530 	struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
531 
532 	/* Accept Port 80h Cycle */
533 	gctrl->GCTRL_SPCTRL1 |= IT8XXX2_GCTRL_ACP80;
534 	IRQ_CONNECT(IT8XXX2_PORT_80_IRQ, 0, port80_it8xxx2_isr,
535 			DEVICE_DT_INST_GET(0), 0);
536 	irq_enable(IT8XXX2_PORT_80_IRQ);
537 }
538 #endif
539 
540 #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
541 /* PMC 2 (Host command port CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM) */
pmc2_it8xxx2_ibf_isr(const struct device * dev)542 static void pmc2_it8xxx2_ibf_isr(const struct device *dev)
543 {
544 	const struct espi_it8xxx2_config *const config = dev->config;
545 	struct espi_it8xxx2_data *const data = dev->data;
546 	struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
547 	struct espi_event evt = {
548 		ESPI_BUS_PERIPHERAL_NOTIFICATION,
549 		ESPI_PERIPHERAL_EC_HOST_CMD,
550 		ESPI_PERIPHERAL_NODATA
551 	};
552 
553 	/* Set processing flag before reading command byte */
554 	pmc_reg->PM2STS |= PMC_PM2STS_GPF;
555 	evt.evt_data = pmc_reg->PM2DI;
556 
557 	espi_send_callbacks(&data->callbacks, dev, evt);
558 }
559 
pmc2_it8xxx2_init(const struct device * dev)560 static void pmc2_it8xxx2_init(const struct device *dev)
561 {
562 	const struct espi_it8xxx2_config *const config = dev->config;
563 	struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
564 
565 	/* Dedicated interrupt for PMC2 */
566 	pmc_reg->MBXCTRL |= PMC_MBXCTRL_DINT;
567 	/* Enable pmc2 input buffer full interrupt */
568 	pmc_reg->PM2CTL |= PMC_PM2CTL_IBFIE;
569 	IRQ_CONNECT(IT8XXX2_PMC2_IBF_IRQ, 0, pmc2_it8xxx2_ibf_isr,
570 			DEVICE_DT_INST_GET(0), 0);
571 	irq_enable(IT8XXX2_PMC2_IBF_IRQ);
572 }
573 #endif
574 
575 /* eSPI api functions */
576 #define VW_CHAN(signal, index, level, valid) \
577 	[signal] = {.vw_index = index, .level_mask = level, .valid_mask = valid}
578 
579 /* VW signals used in eSPI */
580 static const struct vw_channel_t vw_channel_list[] = {
581 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_S3,        0x02, BIT(0), BIT(4)),
582 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_S4,        0x02, BIT(1), BIT(5)),
583 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_S5,        0x02, BIT(2), BIT(6)),
584 	VW_CHAN(ESPI_VWIRE_SIGNAL_OOB_RST_WARN,  0x03, BIT(2), BIT(6)),
585 	VW_CHAN(ESPI_VWIRE_SIGNAL_PLTRST,        0x03, BIT(1), BIT(5)),
586 	VW_CHAN(ESPI_VWIRE_SIGNAL_SUS_STAT,      0x03, BIT(0), BIT(4)),
587 	VW_CHAN(ESPI_VWIRE_SIGNAL_NMIOUT,        0x07, BIT(2), BIT(6)),
588 	VW_CHAN(ESPI_VWIRE_SIGNAL_SMIOUT,        0x07, BIT(1), BIT(5)),
589 	VW_CHAN(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, 0x07, BIT(0), BIT(4)),
590 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_A,         0x41, BIT(3), BIT(7)),
591 	VW_CHAN(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, 0x41, BIT(1), BIT(5)),
592 	VW_CHAN(ESPI_VWIRE_SIGNAL_SUS_WARN,      0x41, BIT(0), BIT(4)),
593 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_WLAN,      0x42, BIT(1), BIT(5)),
594 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLP_LAN,       0x42, BIT(0), BIT(4)),
595 	VW_CHAN(ESPI_VWIRE_SIGNAL_HOST_C10,      0x47, BIT(0), BIT(4)),
596 	VW_CHAN(ESPI_VWIRE_SIGNAL_DNX_WARN,      0x4a, BIT(1), BIT(5)),
597 	VW_CHAN(ESPI_VWIRE_SIGNAL_PME,           0x04, BIT(3), BIT(7)),
598 	VW_CHAN(ESPI_VWIRE_SIGNAL_WAKE,          0x04, BIT(2), BIT(6)),
599 	VW_CHAN(ESPI_VWIRE_SIGNAL_OOB_RST_ACK,   0x04, BIT(0), BIT(4)),
600 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLV_BOOT_STS,  0x05, BIT(3), BIT(7)),
601 	VW_CHAN(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, 0x05, BIT(2), BIT(6)),
602 	VW_CHAN(ESPI_VWIRE_SIGNAL_ERR_FATAL,     0x05, BIT(1), BIT(5)),
603 	VW_CHAN(ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, 0x05, BIT(0), BIT(4)),
604 	VW_CHAN(ESPI_VWIRE_SIGNAL_HOST_RST_ACK,  0x06, BIT(3), BIT(7)),
605 	VW_CHAN(ESPI_VWIRE_SIGNAL_RST_CPU_INIT,  0x06, BIT(2), BIT(6)),
606 	VW_CHAN(ESPI_VWIRE_SIGNAL_SMI,           0x06, BIT(1), BIT(5)),
607 	VW_CHAN(ESPI_VWIRE_SIGNAL_SCI,           0x06, BIT(0), BIT(4)),
608 	VW_CHAN(ESPI_VWIRE_SIGNAL_DNX_ACK,       0x40, BIT(1), BIT(5)),
609 	VW_CHAN(ESPI_VWIRE_SIGNAL_SUS_ACK,       0x40, BIT(0), BIT(4)),
610 };
611 
espi_it8xxx2_configure(const struct device * dev,struct espi_cfg * cfg)612 static int espi_it8xxx2_configure(const struct device *dev,
613 					struct espi_cfg *cfg)
614 {
615 	const struct espi_it8xxx2_config *const config = dev->config;
616 	struct espi_slave_regs *const slave_reg =
617 		(struct espi_slave_regs *)config->base_espi_slave;
618 	uint8_t capcfg1 = 0;
619 
620 	/* Set frequency */
621 	switch (cfg->max_freq) {
622 	case 20:
623 		capcfg1 = IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_20;
624 		break;
625 	case 25:
626 		capcfg1 = IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_25;
627 		break;
628 	case 33:
629 		capcfg1 = IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_33;
630 		break;
631 	case 50:
632 		capcfg1 = IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_50;
633 		break;
634 	case 66:
635 		capcfg1 = IT8XXX2_ESPI_CAPCFG1_MAX_FREQ_66;
636 		break;
637 	default:
638 		return -EINVAL;
639 	}
640 	slave_reg->GCAPCFG1 =
641 		(slave_reg->GCAPCFG1 & ~IT8XXX2_ESPI_MAX_FREQ_MASK) | capcfg1;
642 
643 	/*
644 	 * Configure eSPI I/O mode. (Register read only)
645 	 * Supported I/O mode : single, dual and quad.
646 	 */
647 
648 	/* Configure eSPI supported channels. (Register read only)
649 	 * Supported channels: peripheral, virtual wire, OOB, and flash access.
650 	 */
651 
652 	return 0;
653 }
654 
espi_it8xxx2_channel_ready(const struct device * dev,enum espi_channel ch)655 static bool espi_it8xxx2_channel_ready(const struct device *dev,
656 					enum espi_channel ch)
657 {
658 	const struct espi_it8xxx2_config *const config = dev->config;
659 	struct espi_slave_regs *const slave_reg =
660 		(struct espi_slave_regs *)config->base_espi_slave;
661 	bool sts = false;
662 
663 	switch (ch) {
664 	case ESPI_CHANNEL_PERIPHERAL:
665 		sts = slave_reg->CH_PC_CAPCFG3 & IT8XXX2_ESPI_PC_READY_MASK;
666 		break;
667 	case ESPI_CHANNEL_VWIRE:
668 		sts = slave_reg->CH_VW_CAPCFG3 & IT8XXX2_ESPI_VW_READY_MASK;
669 		break;
670 	case ESPI_CHANNEL_OOB:
671 		sts = slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK;
672 		break;
673 	case ESPI_CHANNEL_FLASH:
674 		sts = slave_reg->CH_FLASH_CAPCFG3 & IT8XXX2_ESPI_FC_READY_MASK;
675 		break;
676 	default:
677 		break;
678 	}
679 
680 	return sts;
681 }
682 
espi_it8xxx2_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)683 static int espi_it8xxx2_send_vwire(const struct device *dev,
684 			enum espi_vwire_signal signal, uint8_t level)
685 {
686 	const struct espi_it8xxx2_config *const config = dev->config;
687 	struct espi_vw_regs *const vw_reg =
688 		(struct espi_vw_regs *)config->base_espi_vw;
689 	uint8_t vw_index = vw_channel_list[signal].vw_index;
690 	uint8_t level_mask = vw_channel_list[signal].level_mask;
691 	uint8_t valid_mask = vw_channel_list[signal].valid_mask;
692 
693 	if (signal > ARRAY_SIZE(vw_channel_list)) {
694 		return -EIO;
695 	}
696 
697 	if (level) {
698 		vw_reg->VW_INDEX[vw_index] |= level_mask;
699 	} else {
700 		vw_reg->VW_INDEX[vw_index] &= ~level_mask;
701 	}
702 
703 	vw_reg->VW_INDEX[vw_index] |= valid_mask;
704 
705 	return 0;
706 }
707 
espi_it8xxx2_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)708 static int espi_it8xxx2_receive_vwire(const struct device *dev,
709 				  enum espi_vwire_signal signal, uint8_t *level)
710 {
711 	const struct espi_it8xxx2_config *const config = dev->config;
712 	struct espi_vw_regs *const vw_reg =
713 		(struct espi_vw_regs *)config->base_espi_vw;
714 	uint8_t vw_index = vw_channel_list[signal].vw_index;
715 	uint8_t level_mask = vw_channel_list[signal].level_mask;
716 	uint8_t valid_mask = vw_channel_list[signal].valid_mask;
717 
718 	if (signal > ARRAY_SIZE(vw_channel_list)) {
719 		return -EIO;
720 	}
721 
722 	if (vw_reg->VW_INDEX[vw_index] & valid_mask) {
723 		*level = !!(vw_reg->VW_INDEX[vw_index] & level_mask);
724 	} else {
725 		/* Not valid */
726 		*level = 0;
727 	}
728 
729 	return 0;
730 }
731 
espi_it8xxx2_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)732 static int espi_it8xxx2_manage_callback(const struct device *dev,
733 				    struct espi_callback *callback, bool set)
734 {
735 	struct espi_it8xxx2_data *const data = dev->data;
736 
737 	return espi_manage_callback(&data->callbacks, callback, set);
738 }
739 
espi_it8xxx2_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)740 static int espi_it8xxx2_read_lpc_request(const struct device *dev,
741 				     enum lpc_peripheral_opcode op,
742 				     uint32_t *data)
743 {
744 	const struct espi_it8xxx2_config *const config = dev->config;
745 
746 	if (op >= E8042_START_OPCODE && op <= E8042_MAX_OPCODE) {
747 		struct kbc_regs *const kbc_reg =
748 			(struct kbc_regs *)config->base_kbc;
749 
750 		switch (op) {
751 		case E8042_OBF_HAS_CHAR:
752 			/* EC has written data back to host. OBF is
753 			 * automatically cleared after host reads
754 			 * the data
755 			 */
756 			*data = !!(kbc_reg->KBHISR & KBC_KBHISR_OBF);
757 			break;
758 		case E8042_IBF_HAS_CHAR:
759 			*data = !!(kbc_reg->KBHISR & KBC_KBHISR_IBF);
760 			break;
761 		case E8042_READ_KB_STS:
762 			*data = kbc_reg->KBHISR;
763 			break;
764 		default:
765 			return -EINVAL;
766 		}
767 	} else if (op >= EACPI_START_OPCODE && op <= EACPI_MAX_OPCODE) {
768 		struct pmc_regs *const pmc_reg =
769 			(struct pmc_regs *)config->base_pmc;
770 
771 		switch (op) {
772 		case EACPI_OBF_HAS_CHAR:
773 			/* EC has written data back to host. OBF is
774 			 * automatically cleared after host reads
775 			 * the data
776 			 */
777 			*data = !!(pmc_reg->PM1STS & PMC_PM1STS_OBF);
778 			break;
779 		case EACPI_IBF_HAS_CHAR:
780 			*data = !!(pmc_reg->PM1STS & PMC_PM1STS_IBF);
781 			break;
782 		case EACPI_READ_STS:
783 			*data = pmc_reg->PM1STS;
784 			break;
785 #ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
786 		case EACPI_GET_SHARED_MEMORY:
787 			*data = (uint32_t)&h2ram_pool[
788 			CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM];
789 			break;
790 #endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
791 		default:
792 			return -EINVAL;
793 		}
794 	}
795 #ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
796 	else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
797 
798 		switch (op) {
799 		case ECUSTOM_HOST_CMD_GET_PARAM_MEMORY:
800 			*data = (uint32_t)&h2ram_pool[
801 				CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM];
802 			break;
803 		case ECUSTOM_HOST_CMD_GET_PARAM_MEMORY_SIZE:
804 			*data = CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE;
805 			break;
806 		default:
807 			return -EINVAL;
808 		}
809 	}
810 #endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
811 	else {
812 		return -ENOTSUP;
813 	}
814 
815 	return 0;
816 }
817 
espi_it8xxx2_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)818 static int espi_it8xxx2_write_lpc_request(const struct device *dev,
819 				      enum lpc_peripheral_opcode op,
820 				      uint32_t *data)
821 {
822 	const struct espi_it8xxx2_config *const config = dev->config;
823 
824 	if (op >= E8042_START_OPCODE && op <= E8042_MAX_OPCODE) {
825 		struct kbc_regs *const kbc_reg =
826 			(struct kbc_regs *)config->base_kbc;
827 
828 		switch (op) {
829 		case E8042_WRITE_KB_CHAR:
830 			kbc_reg->KBHIKDOR = (*data & 0xff);
831 			/*
832 			 * Enable OBE interrupt after putting data in
833 			 * data register.
834 			 */
835 			kbc_reg->KBHICR |= KBC_KBHICR_OBECIE;
836 			break;
837 		case E8042_WRITE_MB_CHAR:
838 			kbc_reg->KBHIMDOR = (*data & 0xff);
839 			/*
840 			 * Enable OBE interrupt after putting data in
841 			 * data register.
842 			 */
843 			kbc_reg->KBHICR |= KBC_KBHICR_OBECIE;
844 			break;
845 		case E8042_RESUME_IRQ:
846 			/* Enable KBC IBF interrupt */
847 			kbc_reg->KBHICR |= KBC_KBHICR_IBFCIE;
848 			break;
849 		case E8042_PAUSE_IRQ:
850 			/* Disable KBC IBF interrupt */
851 			kbc_reg->KBHICR &= ~KBC_KBHICR_IBFCIE;
852 			break;
853 		case E8042_CLEAR_OBF:
854 			/*
855 			 * After enabling IBF/OBF clear mode, we have to make
856 			 * sure that IBF interrupt is not triggered before
857 			 * disabling the clear mode. Or the interrupt will keep
858 			 * triggering until the watchdog is reset.
859 			 */
860 			unsigned int key = irq_lock();
861 			/*
862 			 * When IBFOBFCME is enabled, write 1 to COBF bit to
863 			 * clear KBC OBF.
864 			 */
865 			kbc_reg->KBHICR |= KBC_KBHICR_IBFOBFCME;
866 			kbc_reg->KBHICR |= KBC_KBHICR_COBF;
867 			kbc_reg->KBHICR &= ~KBC_KBHICR_COBF;
868 			/* Disable clear mode */
869 			kbc_reg->KBHICR &= ~KBC_KBHICR_IBFOBFCME;
870 			irq_unlock(key);
871 			break;
872 		case E8042_SET_FLAG:
873 			kbc_reg->KBHISR |= (*data & 0xff);
874 			break;
875 		case E8042_CLEAR_FLAG:
876 			kbc_reg->KBHISR &= ~(*data & 0xff);
877 			break;
878 		default:
879 			return -EINVAL;
880 		}
881 	} else if (op >= EACPI_START_OPCODE && op <= EACPI_MAX_OPCODE) {
882 		struct pmc_regs *const pmc_reg =
883 			(struct pmc_regs *)config->base_pmc;
884 
885 		switch (op) {
886 		case EACPI_WRITE_CHAR:
887 			pmc_reg->PM1DO = (*data & 0xff);
888 			break;
889 		case EACPI_WRITE_STS:
890 			pmc_reg->PM1STS = (*data & 0xff);
891 			break;
892 		default:
893 			return -EINVAL;
894 		}
895 	}
896 #ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
897 	else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
898 		struct pmc_regs *const pmc_reg =
899 			(struct pmc_regs *)config->base_pmc;
900 
901 		switch (op) {
902 		/* Enable/Disable PMC1 (port 62h/66h) interrupt */
903 		case ECUSTOM_HOST_SUBS_INTERRUPT_EN:
904 			if (*data) {
905 				pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE;
906 			} else {
907 				pmc_reg->PM1CTL &= ~PMC_PM1CTL_IBFIE;
908 			}
909 			break;
910 		case ECUSTOM_HOST_CMD_SEND_RESULT:
911 			/* Write result to data output port (set OBF status) */
912 			pmc_reg->PM2DO = (*data & 0xff);
913 			/* Clear processing flag */
914 			pmc_reg->PM2STS &= ~PMC_PM2STS_GPF;
915 			break;
916 		default:
917 			return -EINVAL;
918 		}
919 	}
920 #endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
921 	else {
922 		return -ENOTSUP;
923 	}
924 
925 	return 0;
926 }
927 
928 #ifdef CONFIG_ESPI_OOB_CHANNEL
929 /* eSPI cycle type field */
930 #define ESPI_OOB_CYCLE_TYPE          0x21
931 #define ESPI_OOB_TAG                 0x00
932 #define ESPI_OOB_TIMEOUT_MS          200
933 
934 /* eSPI tag + len[11:8] field */
935 #define ESPI_TAG_LEN_FIELD(tag, len) \
936 		   ((((tag) & 0xF) << 4) | (((len) >> 8) & 0xF))
937 
938 struct espi_oob_msg_packet {
939 	uint8_t data_byte[0];
940 };
941 
espi_it8xxx2_send_oob(const struct device * dev,struct espi_oob_packet * pckt)942 static int espi_it8xxx2_send_oob(const struct device *dev,
943 				struct espi_oob_packet *pckt)
944 {
945 	const struct espi_it8xxx2_config *const config = dev->config;
946 	struct espi_slave_regs *const slave_reg =
947 		(struct espi_slave_regs *)config->base_espi_slave;
948 	struct espi_queue1_regs *const queue1_reg =
949 		(struct espi_queue1_regs *)config->base_espi_queue1;
950 	struct espi_oob_msg_packet *oob_pckt =
951 		(struct espi_oob_msg_packet *)pckt->buf;
952 
953 	if (!(slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK)) {
954 		LOG_ERR("%s: OOB channel isn't ready", __func__);
955 		return -EIO;
956 	}
957 
958 	if (slave_reg->ESUCTRL0 & IT8XXX2_ESPI_UPSTREAM_BUSY) {
959 		LOG_ERR("%s: OOB upstream busy", __func__);
960 		return -EIO;
961 	}
962 
963 	if (pckt->len > ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE) {
964 		LOG_ERR("%s: Out of OOB queue space", __func__);
965 		return -EINVAL;
966 	}
967 
968 	/* Set cycle type */
969 	slave_reg->ESUCTRL1 = IT8XXX2_ESPI_CYCLE_TYPE_OOB;
970 	/* Set tag and length[11:8] */
971 	slave_reg->ESUCTRL2 = ESPI_TAG_LEN_FIELD(0, pckt->len);
972 	/* Set length [7:0] */
973 	slave_reg->ESUCTRL3 = pckt->len & 0xff;
974 
975 	/* Set data byte */
976 	for (int i = 0; i < pckt->len; i++) {
977 		queue1_reg->UPSTREAM_DATA[i] = oob_pckt->data_byte[i];
978 	}
979 
980 	/* Set upstream enable */
981 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE;
982 	/* Set upstream go */
983 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO;
984 
985 	return 0;
986 }
987 
espi_it8xxx2_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)988 static int espi_it8xxx2_receive_oob(const struct device *dev,
989 				struct espi_oob_packet *pckt)
990 {
991 	const struct espi_it8xxx2_config *const config = dev->config;
992 	struct espi_slave_regs *const slave_reg =
993 		(struct espi_slave_regs *)config->base_espi_slave;
994 	struct espi_queue0_regs *const queue0_reg =
995 		(struct espi_queue0_regs *)config->base_espi_queue0;
996 	struct espi_oob_msg_packet *oob_pckt =
997 		(struct espi_oob_msg_packet *)pckt->buf;
998 	uint8_t oob_len;
999 
1000 	if (!(slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK)) {
1001 		LOG_ERR("%s: OOB channel isn't ready", __func__);
1002 		return -EIO;
1003 	}
1004 
1005 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1006 	struct espi_it8xxx2_data *const data = dev->data;
1007 	int ret;
1008 
1009 	/* Wait until receive OOB message or timeout */
1010 	ret = k_sem_take(&data->oob_upstream_go, K_MSEC(ESPI_OOB_TIMEOUT_MS));
1011 	if (ret == -EAGAIN) {
1012 		LOG_ERR("%s: Timeout", __func__);
1013 		return -ETIMEDOUT;
1014 	}
1015 #endif
1016 
1017 	/* Get length */
1018 	oob_len = (slave_reg->ESOCTRL4 & IT8XXX2_ESPI_PUT_OOB_LEN_MASK);
1019 	/*
1020 	 * Buffer passed to driver isn't enough.
1021 	 * The first three bytes of buffer are cycle type, tag, and length.
1022 	 */
1023 	if (oob_len > pckt->len) {
1024 		LOG_ERR("%s: Out of rx buf %d vs %d", __func__,
1025 			oob_len, pckt->len);
1026 		return -EINVAL;
1027 	}
1028 
1029 	pckt->len = oob_len;
1030 	/* Get data byte */
1031 	for (int i = 0; i < oob_len; i++) {
1032 		oob_pckt->data_byte[i] = queue0_reg->PUT_OOB_DATA[i];
1033 	}
1034 
1035 	return 0;
1036 }
1037 
espi_it8xxx2_oob_init(const struct device * dev)1038 static void espi_it8xxx2_oob_init(const struct device *dev)
1039 {
1040 	const struct espi_it8xxx2_config *const config = dev->config;
1041 	struct espi_slave_regs *const slave_reg =
1042 		(struct espi_slave_regs *)config->base_espi_slave;
1043 
1044 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1045 	struct espi_it8xxx2_data *const data = dev->data;
1046 
1047 	k_sem_init(&data->oob_upstream_go, 0, 1);
1048 #endif
1049 
1050 	/* Upstream interrupt enable */
1051 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_INTERRUPT_ENABLE;
1052 
1053 	/* PUT_OOB interrupt enable */
1054 	slave_reg->ESOCTRL1 |= IT8XXX2_ESPI_PUT_OOB_INTERRUPT_ENABLE;
1055 }
1056 #endif
1057 
1058 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1059 #define ESPI_FLASH_TAG                      0x01
1060 #define ESPI_FLASH_READ_TIMEOUT_MS          200
1061 #define ESPI_FLASH_WRITE_TIMEOUT_MS         500
1062 #define ESPI_FLASH_ERASE_TIMEOUT_MS         1000
1063 
1064 /* Successful completion without data */
1065 #define ESPI_IT8XXX2_PUT_FLASH_C_SCWOD      0
1066 /* Successful completion with data */
1067 #define ESPI_IT8XXX2_PUT_FLASH_C_SCWD       4
1068 
1069 enum espi_flash_cycle_type {
1070 	IT8XXX2_ESPI_CYCLE_TYPE_FLASH_READ = 0x08,
1071 	IT8XXX2_ESPI_CYCLE_TYPE_FLASH_WRITE = 0x09,
1072 	IT8XXX2_ESPI_CYCLE_TYPE_FLASH_ERASE = 0x0A,
1073 };
1074 
espi_it8xxx2_flash_trans(const struct device * dev,struct espi_flash_packet * pckt,enum espi_flash_cycle_type tran)1075 static int espi_it8xxx2_flash_trans(const struct device *dev,
1076 				struct espi_flash_packet *pckt,
1077 				enum espi_flash_cycle_type tran)
1078 {
1079 	const struct espi_it8xxx2_config *const config = dev->config;
1080 	struct espi_slave_regs *const slave_reg =
1081 		(struct espi_slave_regs *)config->base_espi_slave;
1082 	struct espi_queue1_regs *const queue1_reg =
1083 		(struct espi_queue1_regs *)config->base_espi_queue1;
1084 
1085 	if (!(slave_reg->CH_FLASH_CAPCFG3 & IT8XXX2_ESPI_FC_READY_MASK)) {
1086 		LOG_ERR("%s: Flash channel isn't ready (tran:%d)",
1087 			__func__, tran);
1088 		return -EIO;
1089 	}
1090 
1091 	if (slave_reg->ESUCTRL0 & IT8XXX2_ESPI_UPSTREAM_BUSY) {
1092 		LOG_ERR("%s: Upstream busy (tran:%d)", __func__, tran);
1093 		return -EIO;
1094 	}
1095 
1096 	if (pckt->len > IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE) {
1097 		LOG_ERR("%s: Invalid size request (tran:%d)", __func__, tran);
1098 		return -EINVAL;
1099 	}
1100 
1101 	/* Set cycle type */
1102 	slave_reg->ESUCTRL1 = tran;
1103 	/* Set tag and length[11:8] */
1104 	slave_reg->ESUCTRL2 = (ESPI_FLASH_TAG << 4);
1105 	/*
1106 	 * Set length [7:0]
1107 	 * Note: for erasing, the least significant 3 bit of the length field
1108 	 * specifies the size of the block to be erased:
1109 	 * 001b: 4 Kbytes
1110 	 * 010b: 64Kbytes
1111 	 * 100b: 128 Kbytes
1112 	 * 101b: 256 Kbytes
1113 	 */
1114 	slave_reg->ESUCTRL3 = pckt->len;
1115 	/* Set flash address */
1116 	queue1_reg->UPSTREAM_DATA[0] = (pckt->flash_addr >> 24) & 0xff;
1117 	queue1_reg->UPSTREAM_DATA[1] = (pckt->flash_addr >> 16) & 0xff;
1118 	queue1_reg->UPSTREAM_DATA[2] = (pckt->flash_addr >> 8) & 0xff;
1119 	queue1_reg->UPSTREAM_DATA[3] = pckt->flash_addr & 0xff;
1120 
1121 	return 0;
1122 }
1123 
espi_it8xxx2_flash_read(const struct device * dev,struct espi_flash_packet * pckt)1124 static int espi_it8xxx2_flash_read(const struct device *dev,
1125 					struct espi_flash_packet *pckt)
1126 {
1127 	const struct espi_it8xxx2_config *const config = dev->config;
1128 	struct espi_it8xxx2_data *const data = dev->data;
1129 	struct espi_slave_regs *const slave_reg =
1130 		(struct espi_slave_regs *)config->base_espi_slave;
1131 	int ret;
1132 
1133 	ret = espi_it8xxx2_flash_trans(dev, pckt,
1134 					IT8XXX2_ESPI_CYCLE_TYPE_FLASH_READ);
1135 	if (ret) {
1136 		return ret;
1137 	}
1138 
1139 	/* Set upstream enable */
1140 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE;
1141 	/* Set upstream go */
1142 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO;
1143 
1144 	/* Wait until upstream done or timeout */
1145 	ret = k_sem_take(&data->flash_upstream_go,
1146 			K_MSEC(ESPI_FLASH_READ_TIMEOUT_MS));
1147 	if (ret == -EAGAIN) {
1148 		LOG_ERR("%s: Timeout", __func__);
1149 		return -ETIMEDOUT;
1150 	}
1151 
1152 	if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWD) {
1153 		LOG_ERR("%s: Unsuccessful completion", __func__);
1154 		return -EIO;
1155 	}
1156 
1157 	memcpy(pckt->buf, data->flash_buf, pckt->len);
1158 
1159 	LOG_INF("%s: read (%d) bytes from flash over espi", __func__,
1160 		data->put_flash_len);
1161 
1162 	return 0;
1163 }
1164 
espi_it8xxx2_flash_write(const struct device * dev,struct espi_flash_packet * pckt)1165 static int espi_it8xxx2_flash_write(const struct device *dev,
1166 					struct espi_flash_packet *pckt)
1167 {
1168 	const struct espi_it8xxx2_config *const config = dev->config;
1169 	struct espi_it8xxx2_data *const data = dev->data;
1170 	struct espi_slave_regs *const slave_reg =
1171 		(struct espi_slave_regs *)config->base_espi_slave;
1172 	struct espi_queue1_regs *const queue1_reg =
1173 		(struct espi_queue1_regs *)config->base_espi_queue1;
1174 	int ret;
1175 
1176 	ret = espi_it8xxx2_flash_trans(dev, pckt,
1177 					IT8XXX2_ESPI_CYCLE_TYPE_FLASH_WRITE);
1178 	if (ret) {
1179 		return ret;
1180 	}
1181 
1182 	/* Set data byte */
1183 	for (int i = 0; i < pckt->len; i++) {
1184 		queue1_reg->UPSTREAM_DATA[4 + i] = pckt->buf[i];
1185 	}
1186 
1187 	/* Set upstream enable */
1188 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE;
1189 	/* Set upstream go */
1190 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO;
1191 
1192 	/* Wait until upstream done or timeout */
1193 	ret = k_sem_take(&data->flash_upstream_go,
1194 			K_MSEC(ESPI_FLASH_WRITE_TIMEOUT_MS));
1195 	if (ret == -EAGAIN) {
1196 		LOG_ERR("%s: Timeout", __func__);
1197 		return -ETIMEDOUT;
1198 	}
1199 
1200 	if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWOD) {
1201 		LOG_ERR("%s: Unsuccessful completion", __func__);
1202 		return -EIO;
1203 	}
1204 
1205 	return 0;
1206 }
1207 
espi_it8xxx2_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)1208 static int espi_it8xxx2_flash_erase(const struct device *dev,
1209 					struct espi_flash_packet *pckt)
1210 {
1211 	const struct espi_it8xxx2_config *const config = dev->config;
1212 	struct espi_it8xxx2_data *const data = dev->data;
1213 	struct espi_slave_regs *const slave_reg =
1214 		(struct espi_slave_regs *)config->base_espi_slave;
1215 	int ret;
1216 
1217 	ret = espi_it8xxx2_flash_trans(dev, pckt,
1218 					IT8XXX2_ESPI_CYCLE_TYPE_FLASH_ERASE);
1219 	if (ret) {
1220 		return ret;
1221 	}
1222 
1223 	/* Set upstream enable */
1224 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE;
1225 	/* Set upstream go */
1226 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO;
1227 
1228 	/* Wait until upstream done or timeout */
1229 	ret = k_sem_take(&data->flash_upstream_go,
1230 			K_MSEC(ESPI_FLASH_ERASE_TIMEOUT_MS));
1231 	if (ret == -EAGAIN) {
1232 		LOG_ERR("%s: Timeout", __func__);
1233 		return -ETIMEDOUT;
1234 	}
1235 
1236 	if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWOD) {
1237 		LOG_ERR("%s: Unsuccessful completion", __func__);
1238 		return -EIO;
1239 	}
1240 
1241 	return 0;
1242 }
1243 
espi_it8xxx2_flash_upstream_done_isr(const struct device * dev)1244 static void espi_it8xxx2_flash_upstream_done_isr(const struct device *dev)
1245 {
1246 	const struct espi_it8xxx2_config *const config = dev->config;
1247 	struct espi_it8xxx2_data *const data = dev->data;
1248 	struct espi_slave_regs *const slave_reg =
1249 		(struct espi_slave_regs *)config->base_espi_slave;
1250 	struct espi_queue1_regs *const queue1_reg =
1251 		(struct espi_queue1_regs *)config->base_espi_queue1;
1252 
1253 	data->put_flash_cycle_type = slave_reg->ESUCTRL6;
1254 	data->put_flash_tag = slave_reg->ESUCTRL7 &
1255 				IT8XXX2_ESPI_PUT_FLASH_TAG_MASK;
1256 	data->put_flash_len = slave_reg->ESUCTRL8 &
1257 				IT8XXX2_ESPI_PUT_FLASH_LEN_MASK;
1258 
1259 	if (slave_reg->ESUCTRL1 == IT8XXX2_ESPI_CYCLE_TYPE_FLASH_READ) {
1260 		if (data->put_flash_len > IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE) {
1261 			LOG_ERR("%s: Invalid size (%d)", __func__,
1262 							data->put_flash_len);
1263 		} else {
1264 			for (int i = 0; i < data->put_flash_len; i++) {
1265 				data->flash_buf[i] =
1266 					queue1_reg->UPSTREAM_DATA[i];
1267 			}
1268 		}
1269 	}
1270 
1271 	k_sem_give(&data->flash_upstream_go);
1272 }
1273 
espi_it8xxx2_flash_init(const struct device * dev)1274 static void espi_it8xxx2_flash_init(const struct device *dev)
1275 {
1276 	const struct espi_it8xxx2_config *const config = dev->config;
1277 	struct espi_it8xxx2_data *const data = dev->data;
1278 	struct espi_slave_regs *const slave_reg =
1279 		(struct espi_slave_regs *)config->base_espi_slave;
1280 
1281 	k_sem_init(&data->flash_upstream_go, 0, 1);
1282 
1283 	/* Upstream interrupt enable */
1284 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_INTERRUPT_ENABLE;
1285 }
1286 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
1287 
1288 /* eSPI driver registration */
1289 static int espi_it8xxx2_init(const struct device *dev);
1290 
1291 static const struct espi_driver_api espi_it8xxx2_driver_api = {
1292 	.config = espi_it8xxx2_configure,
1293 	.get_channel_status = espi_it8xxx2_channel_ready,
1294 	.send_vwire = espi_it8xxx2_send_vwire,
1295 	.receive_vwire = espi_it8xxx2_receive_vwire,
1296 	.manage_callback = espi_it8xxx2_manage_callback,
1297 	.read_lpc_request = espi_it8xxx2_read_lpc_request,
1298 	.write_lpc_request = espi_it8xxx2_write_lpc_request,
1299 #ifdef CONFIG_ESPI_OOB_CHANNEL
1300 	.send_oob = espi_it8xxx2_send_oob,
1301 	.receive_oob = espi_it8xxx2_receive_oob,
1302 #endif
1303 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1304 	.flash_read = espi_it8xxx2_flash_read,
1305 	.flash_write = espi_it8xxx2_flash_write,
1306 	.flash_erase = espi_it8xxx2_flash_erase,
1307 #endif
1308 };
1309 
espi_it8xxx2_vw_notify_system_state(const struct device * dev,enum espi_vwire_signal signal)1310 static void espi_it8xxx2_vw_notify_system_state(const struct device *dev,
1311 				enum espi_vwire_signal signal)
1312 {
1313 	struct espi_it8xxx2_data *const data = dev->data;
1314 	struct espi_event evt = {ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0};
1315 	uint8_t level = 0;
1316 
1317 	espi_it8xxx2_receive_vwire(dev, signal, &level);
1318 
1319 	evt.evt_details = signal;
1320 	evt.evt_data = level;
1321 	espi_send_callbacks(&data->callbacks, dev, evt);
1322 }
1323 
espi_vw_signal_no_isr(const struct device * dev)1324 static void espi_vw_signal_no_isr(const struct device *dev)
1325 {
1326 	ARG_UNUSED(dev);
1327 }
1328 
1329 static const struct espi_vw_signal_t vwidx2_signals[] = {
1330 	{ESPI_VWIRE_SIGNAL_SLP_S3, NULL},
1331 	{ESPI_VWIRE_SIGNAL_SLP_S4, NULL},
1332 	{ESPI_VWIRE_SIGNAL_SLP_S5, NULL},
1333 };
1334 
espi_it8xxx2_vwidx2_isr(const struct device * dev,uint8_t updated_flag)1335 static void espi_it8xxx2_vwidx2_isr(const struct device *dev,
1336 					uint8_t updated_flag)
1337 {
1338 	for (int i = 0; i < ARRAY_SIZE(vwidx2_signals); i++) {
1339 		enum espi_vwire_signal vw_signal = vwidx2_signals[i].signal;
1340 
1341 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1342 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1343 		}
1344 	}
1345 }
1346 
espi_vw_oob_rst_warn_isr(const struct device * dev)1347 static void espi_vw_oob_rst_warn_isr(const struct device *dev)
1348 {
1349 	uint8_t level = 0;
1350 
1351 	espi_it8xxx2_receive_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_WARN, &level);
1352 	espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK, level);
1353 }
1354 
espi_vw_pltrst_isr(const struct device * dev)1355 static void espi_vw_pltrst_isr(const struct device *dev)
1356 {
1357 	uint8_t pltrst = 0;
1358 
1359 	espi_it8xxx2_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &pltrst);
1360 
1361 	if (pltrst) {
1362 		espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_SMI, 1);
1363 		espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_SCI, 1);
1364 		espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_HOST_RST_ACK, 1);
1365 		espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_RST_CPU_INIT, 1);
1366 	}
1367 
1368 	LOG_INF("VW PLTRST_L %sasserted", pltrst ? "de" : "");
1369 }
1370 
1371 static const struct espi_vw_signal_t vwidx3_signals[] = {
1372 	{ESPI_VWIRE_SIGNAL_OOB_RST_WARN, espi_vw_oob_rst_warn_isr},
1373 	{ESPI_VWIRE_SIGNAL_PLTRST,       espi_vw_pltrst_isr},
1374 };
1375 
espi_it8xxx2_vwidx3_isr(const struct device * dev,uint8_t updated_flag)1376 static void espi_it8xxx2_vwidx3_isr(const struct device *dev,
1377 					uint8_t updated_flag)
1378 {
1379 	for (int i = 0; i < ARRAY_SIZE(vwidx3_signals); i++) {
1380 		enum espi_vwire_signal vw_signal = vwidx3_signals[i].signal;
1381 
1382 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1383 			vwidx3_signals[i].vw_signal_isr(dev);
1384 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1385 		}
1386 	}
1387 }
1388 
espi_vw_host_rst_warn_isr(const struct device * dev)1389 static void espi_vw_host_rst_warn_isr(const struct device *dev)
1390 {
1391 	uint8_t level = 0;
1392 
1393 	espi_it8xxx2_receive_vwire(dev,
1394 		ESPI_VWIRE_SIGNAL_HOST_RST_WARN, &level);
1395 	espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_HOST_RST_ACK, level);
1396 }
1397 
1398 static const struct espi_vw_signal_t vwidx7_signals[] = {
1399 	{ESPI_VWIRE_SIGNAL_HOST_RST_WARN, espi_vw_host_rst_warn_isr},
1400 };
1401 
espi_it8xxx2_vwidx7_isr(const struct device * dev,uint8_t updated_flag)1402 static void espi_it8xxx2_vwidx7_isr(const struct device *dev,
1403 					uint8_t updated_flag)
1404 {
1405 	for (int i = 0; i < ARRAY_SIZE(vwidx7_signals); i++) {
1406 		enum espi_vwire_signal vw_signal = vwidx7_signals[i].signal;
1407 
1408 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1409 			vwidx7_signals[i].vw_signal_isr(dev);
1410 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1411 		}
1412 	}
1413 }
1414 
espi_vw_sus_warn_isr(const struct device * dev)1415 static void espi_vw_sus_warn_isr(const struct device *dev)
1416 {
1417 	uint8_t level = 0;
1418 
1419 	espi_it8xxx2_receive_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_WARN, &level);
1420 	espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK, level);
1421 }
1422 
1423 static const struct espi_vw_signal_t vwidx41_signals[] = {
1424 	{ESPI_VWIRE_SIGNAL_SUS_WARN,      espi_vw_sus_warn_isr},
1425 	{ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, espi_vw_signal_no_isr},
1426 	{ESPI_VWIRE_SIGNAL_SLP_A,         espi_vw_signal_no_isr},
1427 };
1428 
espi_it8xxx2_vwidx41_isr(const struct device * dev,uint8_t updated_flag)1429 static void espi_it8xxx2_vwidx41_isr(const struct device *dev,
1430 					uint8_t updated_flag)
1431 {
1432 	for (int i = 0; i < ARRAY_SIZE(vwidx41_signals); i++) {
1433 		enum espi_vwire_signal vw_signal = vwidx41_signals[i].signal;
1434 
1435 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1436 			vwidx41_signals[i].vw_signal_isr(dev);
1437 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1438 		}
1439 	}
1440 }
1441 
1442 static const struct espi_vw_signal_t vwidx42_signals[] = {
1443 	{ESPI_VWIRE_SIGNAL_SLP_LAN, NULL},
1444 	{ESPI_VWIRE_SIGNAL_SLP_WLAN, NULL},
1445 };
1446 
espi_it8xxx2_vwidx42_isr(const struct device * dev,uint8_t updated_flag)1447 static void espi_it8xxx2_vwidx42_isr(const struct device *dev,
1448 					uint8_t updated_flag)
1449 {
1450 	for (int i = 0; i < ARRAY_SIZE(vwidx42_signals); i++) {
1451 		enum espi_vwire_signal vw_signal = vwidx42_signals[i].signal;
1452 
1453 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1454 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1455 		}
1456 	}
1457 }
1458 
espi_it8xxx2_vwidx43_isr(const struct device * dev,uint8_t updated_flag)1459 static void espi_it8xxx2_vwidx43_isr(const struct device *dev,
1460 					uint8_t updated_flag)
1461 {
1462 	ARG_UNUSED(dev);
1463 	/*
1464 	 * We haven't send callback to system because there is no index 43
1465 	 * virtual wire signal is listed in enum espi_vwire_signal.
1466 	 */
1467 	LOG_INF("vw isr %s is ignored!", __func__);
1468 }
1469 
espi_it8xxx2_vwidx44_isr(const struct device * dev,uint8_t updated_flag)1470 static void espi_it8xxx2_vwidx44_isr(const struct device *dev,
1471 					uint8_t updated_flag)
1472 {
1473 	ARG_UNUSED(dev);
1474 	/*
1475 	 * We haven't send callback to system because there is no index 44
1476 	 * virtual wire signal is listed in enum espi_vwire_signal.
1477 	 */
1478 	LOG_INF("vw isr %s is ignored!", __func__);
1479 }
1480 
1481 static const struct espi_vw_signal_t vwidx47_signals[] = {
1482 	{ESPI_VWIRE_SIGNAL_HOST_C10, NULL},
1483 };
espi_it8xxx2_vwidx47_isr(const struct device * dev,uint8_t updated_flag)1484 static void espi_it8xxx2_vwidx47_isr(const struct device *dev,
1485 					uint8_t updated_flag)
1486 {
1487 	for (int i = 0; i < ARRAY_SIZE(vwidx47_signals); i++) {
1488 		enum espi_vwire_signal vw_signal = vwidx47_signals[i].signal;
1489 
1490 		if (updated_flag & vw_channel_list[vw_signal].level_mask) {
1491 			espi_it8xxx2_vw_notify_system_state(dev, vw_signal);
1492 		}
1493 	}
1494 }
1495 
1496 /*
1497  * The ISR of espi VW interrupt in array needs to match bit order in
1498  * ESPI VW VWCTRL1 register.
1499  */
1500 static const struct vwidx_isr_t vwidx_isr_list[] = {
1501 	[0] = {espi_it8xxx2_vwidx2_isr,  0x02},
1502 	[1] = {espi_it8xxx2_vwidx3_isr,  0x03},
1503 	[2] = {espi_it8xxx2_vwidx7_isr,  0x07},
1504 	[3] = {espi_it8xxx2_vwidx41_isr, 0x41},
1505 	[4] = {espi_it8xxx2_vwidx42_isr, 0x42},
1506 	[5] = {espi_it8xxx2_vwidx43_isr, 0x43},
1507 	[6] = {espi_it8xxx2_vwidx44_isr, 0x44},
1508 	[7] = {espi_it8xxx2_vwidx47_isr, 0x47},
1509 };
1510 
1511 /*
1512  * This is used to record the previous VW valid/level field state to discover
1513  * changes. Then do following sequence only when state is changed.
1514  */
1515 static uint8_t vwidx_cached_flag[ARRAY_SIZE(vwidx_isr_list)];
1516 
espi_it8xxx2_reset_vwidx_cache(const struct device * dev)1517 static void espi_it8xxx2_reset_vwidx_cache(const struct device *dev)
1518 {
1519 	const struct espi_it8xxx2_config *const config = dev->config;
1520 	struct espi_vw_regs *const vw_reg =
1521 		(struct espi_vw_regs *)config->base_espi_vw;
1522 
1523 	/* reset vwidx_cached_flag */
1524 	for (int i = 0; i < ARRAY_SIZE(vwidx_isr_list); i++) {
1525 		vwidx_cached_flag[i] =
1526 			vw_reg->VW_INDEX[vwidx_isr_list[i].vw_index];
1527 	}
1528 }
1529 
espi_it8xxx2_vw_isr(const struct device * dev)1530 static void espi_it8xxx2_vw_isr(const struct device *dev)
1531 {
1532 	const struct espi_it8xxx2_config *const config = dev->config;
1533 	struct espi_vw_regs *const vw_reg =
1534 		(struct espi_vw_regs *)config->base_espi_vw;
1535 	uint8_t vwidx_updated = vw_reg->VWCTRL1;
1536 
1537 	/* write-1 to clear */
1538 	vw_reg->VWCTRL1 = vwidx_updated;
1539 
1540 	for (int i = 0; i < ARRAY_SIZE(vwidx_isr_list); i++) {
1541 		if (vwidx_updated & BIT(i)) {
1542 			uint8_t vw_flag;
1543 
1544 			vw_flag = vw_reg->VW_INDEX[vwidx_isr_list[i].vw_index];
1545 			vwidx_isr_list[i].vwidx_isr(dev,
1546 					vwidx_cached_flag[i] ^ vw_flag);
1547 			vwidx_cached_flag[i] = vw_flag;
1548 		}
1549 	}
1550 }
1551 
espi_it8xxx2_ch_notify_system_state(const struct device * dev,enum espi_channel ch,bool en)1552 static void espi_it8xxx2_ch_notify_system_state(const struct device *dev,
1553 						enum espi_channel ch, bool en)
1554 {
1555 	struct espi_it8xxx2_data *const data = dev->data;
1556 	struct espi_event evt = {
1557 		.evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
1558 		.evt_details = ch,
1559 		.evt_data = en,
1560 	};
1561 
1562 	espi_send_callbacks(&data->callbacks, dev, evt);
1563 }
1564 
1565 /*
1566  * Peripheral channel enable asserted flag.
1567  * A 0-to-1 or 1-to-0 transition on "Peripheral Channel Enable" bit.
1568  */
espi_it8xxx2_peripheral_ch_en_isr(const struct device * dev,bool enable)1569 static void espi_it8xxx2_peripheral_ch_en_isr(const struct device *dev,
1570 						bool enable)
1571 {
1572 	espi_it8xxx2_ch_notify_system_state(dev,
1573 					ESPI_CHANNEL_PERIPHERAL, enable);
1574 }
1575 
1576 /*
1577  * VW channel enable asserted flag.
1578  * A 0-to-1 or 1-to-0 transition on "Virtual Wire Channel Enable" bit.
1579  */
espi_it8xxx2_vw_ch_en_isr(const struct device * dev,bool enable)1580 static void espi_it8xxx2_vw_ch_en_isr(const struct device *dev, bool enable)
1581 {
1582 	espi_it8xxx2_ch_notify_system_state(dev, ESPI_CHANNEL_VWIRE, enable);
1583 }
1584 
1585 /*
1586  * OOB message channel enable asserted flag.
1587  * A 0-to-1 or 1-to-0 transition on "OOB Message Channel Enable" bit.
1588  */
espi_it8xxx2_oob_ch_en_isr(const struct device * dev,bool enable)1589 static void espi_it8xxx2_oob_ch_en_isr(const struct device *dev, bool enable)
1590 {
1591 	espi_it8xxx2_ch_notify_system_state(dev, ESPI_CHANNEL_OOB, enable);
1592 }
1593 
1594 /*
1595  * Flash channel enable asserted flag.
1596  * A 0-to-1 or 1-to-0 transition on "Flash Access Channel Enable" bit.
1597  */
espi_it8xxx2_flash_ch_en_isr(const struct device * dev,bool enable)1598 static void espi_it8xxx2_flash_ch_en_isr(const struct device *dev, bool enable)
1599 {
1600 	if (enable) {
1601 		espi_it8xxx2_send_vwire(dev, ESPI_VWIRE_SIGNAL_SLV_BOOT_STS, 1);
1602 		espi_it8xxx2_send_vwire(dev,
1603 					ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, 1);
1604 	}
1605 
1606 	espi_it8xxx2_ch_notify_system_state(dev, ESPI_CHANNEL_FLASH, enable);
1607 }
1608 
espi_it8xxx2_put_pc_status_isr(const struct device * dev)1609 static void espi_it8xxx2_put_pc_status_isr(const struct device *dev)
1610 {
1611 	const struct espi_it8xxx2_config *const config = dev->config;
1612 	struct espi_slave_regs *const slave_reg =
1613 		(struct espi_slave_regs *)config->base_espi_slave;
1614 
1615 	/*
1616 	 * TODO: To check cycle type (bit[3-0] at ESPCTRL0) and make
1617 	 * corresponding modification if needed.
1618 	 */
1619 	LOG_INF("isr %s is ignored!", __func__);
1620 
1621 	/* write-1-clear to release PC_FREE */
1622 	slave_reg->ESPCTRL0 = IT8XXX2_ESPI_INTERRUPT_PUT_PC;
1623 }
1624 
1625 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_it8xxx2_upstream_channel_disable_isr(const struct device * dev)1626 static void espi_it8xxx2_upstream_channel_disable_isr(const struct device *dev)
1627 {
1628 	const struct espi_it8xxx2_config *const config = dev->config;
1629 	struct espi_slave_regs *const slave_reg =
1630 		(struct espi_slave_regs *)config->base_espi_slave;
1631 
1632 	LOG_INF("isr %s is ignored!", __func__);
1633 
1634 	/* write-1 to clear this bit */
1635 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_CHANNEL_DISABLE;
1636 }
1637 
espi_it8xxx2_put_oob_status_isr(const struct device * dev)1638 static void espi_it8xxx2_put_oob_status_isr(const struct device *dev)
1639 {
1640 	const struct espi_it8xxx2_config *const config = dev->config;
1641 	struct espi_it8xxx2_data *const data = dev->data;
1642 	struct espi_slave_regs *const slave_reg =
1643 		(struct espi_slave_regs *)config->base_espi_slave;
1644 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1645 	struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
1646 				  .evt_details = 0,
1647 				  .evt_data = 0 };
1648 #endif
1649 
1650 	/* Write-1 to clear this bit for the next coming posted transaction. */
1651 	slave_reg->ESOCTRL0 |= IT8XXX2_ESPI_PUT_OOB_STATUS;
1652 
1653 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1654 	k_sem_give(&data->oob_upstream_go);
1655 #else
1656 	/* Additional detail is length field of PUT_OOB message packet. */
1657 	evt.evt_details = (slave_reg->ESOCTRL4 & IT8XXX2_ESPI_PUT_OOB_LEN_MASK);
1658 	espi_send_callbacks(&data->callbacks, dev, evt);
1659 #endif
1660 }
1661 #endif
1662 
1663 #if defined(CONFIG_ESPI_OOB_CHANNEL) || defined(CONFIG_ESPI_FLASH_CHANNEL)
espi_it8xxx2_upstream_done_isr(const struct device * dev)1664 static void espi_it8xxx2_upstream_done_isr(const struct device *dev)
1665 {
1666 	const struct espi_it8xxx2_config *const config = dev->config;
1667 	struct espi_slave_regs *const slave_reg =
1668 		(struct espi_slave_regs *)config->base_espi_slave;
1669 
1670 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1671 	/* cycle type is flash read, write, or erase */
1672 	if (slave_reg->ESUCTRL1 != IT8XXX2_ESPI_CYCLE_TYPE_OOB) {
1673 		espi_it8xxx2_flash_upstream_done_isr(dev);
1674 	}
1675 #endif
1676 
1677 	/* write-1 to clear this bit */
1678 	slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_DONE;
1679 	/* upstream disable */
1680 	slave_reg->ESUCTRL0 &= ~IT8XXX2_ESPI_UPSTREAM_ENABLE;
1681 }
1682 #endif
1683 
1684 /*
1685  * The ISR of espi interrupt event in array need to be matched bit order in
1686  * IT8XXX2 ESPI ESGCTRL0 register.
1687  */
1688 static const struct espi_isr_t espi_isr_list[] = {
1689 	[0] = {espi_it8xxx2_peripheral_ch_en_isr, ASSERTED_FLAG},
1690 	[1] = {espi_it8xxx2_vw_ch_en_isr,         ASSERTED_FLAG},
1691 	[2] = {espi_it8xxx2_oob_ch_en_isr,        ASSERTED_FLAG},
1692 	[3] = {espi_it8xxx2_flash_ch_en_isr,      ASSERTED_FLAG},
1693 	[4] = {espi_it8xxx2_peripheral_ch_en_isr, DEASSERTED_FLAG},
1694 	[5] = {espi_it8xxx2_vw_ch_en_isr,         DEASSERTED_FLAG},
1695 	[6] = {espi_it8xxx2_oob_ch_en_isr,        DEASSERTED_FLAG},
1696 	[7] = {espi_it8xxx2_flash_ch_en_isr,      DEASSERTED_FLAG},
1697 };
1698 
espi_it8xxx2_isr(const struct device * dev)1699 static void espi_it8xxx2_isr(const struct device *dev)
1700 {
1701 	const struct espi_it8xxx2_config *const config = dev->config;
1702 	struct espi_slave_regs *const slave_reg =
1703 		(struct espi_slave_regs *)config->base_espi_slave;
1704 	/* get espi interrupt events */
1705 	uint8_t espi_event = slave_reg->ESGCTRL0;
1706 #if defined(CONFIG_ESPI_OOB_CHANNEL) || defined(CONFIG_ESPI_FLASH_CHANNEL)
1707 	uint8_t espi_upstream = slave_reg->ESUCTRL0;
1708 #endif
1709 
1710 	/* write-1 to clear */
1711 	slave_reg->ESGCTRL0 = espi_event;
1712 
1713 	/* process espi interrupt events */
1714 	for (int i = 0; i < ARRAY_SIZE(espi_isr_list); i++) {
1715 		if (espi_event & BIT(i)) {
1716 			espi_isr_list[i].espi_isr(dev,
1717 				espi_isr_list[i].isr_type);
1718 		}
1719 	}
1720 
1721 	/*
1722 	 * bit7: the peripheral has received a peripheral posted/completion.
1723 	 * This bit indicates the peripheral has received a packet from eSPI
1724 	 * peripheral channel.
1725 	 */
1726 	if (slave_reg->ESPCTRL0 & IT8XXX2_ESPI_INTERRUPT_PUT_PC) {
1727 		espi_it8xxx2_put_pc_status_isr(dev);
1728 	}
1729 
1730 #ifdef CONFIG_ESPI_OOB_CHANNEL
1731 	/*
1732 	 * The corresponding channel of the eSPI upstream transaction is
1733 	 * disabled.
1734 	 */
1735 	if (espi_upstream & IT8XXX2_ESPI_UPSTREAM_CHANNEL_DISABLE) {
1736 		espi_it8xxx2_upstream_channel_disable_isr(dev);
1737 	}
1738 
1739 	/* The eSPI slave has received a PUT_OOB message. */
1740 	if (slave_reg->ESOCTRL0 & IT8XXX2_ESPI_PUT_OOB_STATUS) {
1741 		espi_it8xxx2_put_oob_status_isr(dev);
1742 	}
1743 #endif
1744 
1745 	/* eSPI oob and flash channels use the same interrupt of upstream. */
1746 #if defined(CONFIG_ESPI_OOB_CHANNEL) || defined(CONFIG_ESPI_FLASH_CHANNEL)
1747 	/* The eSPI upstream transaction is done. */
1748 	if (espi_upstream & IT8XXX2_ESPI_UPSTREAM_DONE) {
1749 		espi_it8xxx2_upstream_done_isr(dev);
1750 	}
1751 #endif
1752 }
1753 
espi_it8xxx2_enable_pad_ctrl(const struct device * dev,bool enable)1754 void espi_it8xxx2_enable_pad_ctrl(const struct device *dev, bool enable)
1755 {
1756 	const struct espi_it8xxx2_config *const config = dev->config;
1757 	struct espi_slave_regs *const slave_reg =
1758 		(struct espi_slave_regs *)config->base_espi_slave;
1759 
1760 	if (enable) {
1761 		/* Enable eSPI pad. */
1762 		slave_reg->ESGCTRL2 &= ~IT8XXX2_ESPI_INPUT_PAD_GATING;
1763 	} else {
1764 		/* Disable eSPI pad. */
1765 		slave_reg->ESGCTRL2 |= IT8XXX2_ESPI_INPUT_PAD_GATING;
1766 	}
1767 }
1768 
espi_it8xxx2_enable_trans_irq(const struct device * dev,bool enable)1769 void espi_it8xxx2_enable_trans_irq(const struct device *dev, bool enable)
1770 {
1771 	const struct espi_it8xxx2_config *const config = dev->config;
1772 
1773 	if (enable) {
1774 		irq_enable(IT8XXX2_TRANS_IRQ);
1775 	} else {
1776 		irq_disable(IT8XXX2_TRANS_IRQ);
1777 		/* Clear pending interrupt */
1778 		it8xxx2_wuc_clear_status(config->wuc.wucs, config->wuc.mask);
1779 	}
1780 }
1781 
espi_it8xxx2_trans_isr(const struct device * dev)1782 static void espi_it8xxx2_trans_isr(const struct device *dev)
1783 {
1784 	/*
1785 	 * This interrupt is only used to wake up CPU, there is no need to do
1786 	 * anything in the isr in addition to disable interrupt.
1787 	 */
1788 	espi_it8xxx2_enable_trans_irq(dev, false);
1789 }
1790 
espi_it8xxx2_espi_reset_isr(const struct device * port,struct gpio_callback * cb,uint32_t pins)1791 void espi_it8xxx2_espi_reset_isr(const struct device *port,
1792 				struct gpio_callback *cb, uint32_t pins)
1793 {
1794 	struct espi_it8xxx2_data *const data = ESPI_IT8XXX2_SOC_DEV->data;
1795 	struct espi_event evt = {ESPI_BUS_RESET, 0, 0};
1796 	bool espi_reset = gpio_pin_get(port, (find_msb_set(pins) - 1));
1797 
1798 	if (!(espi_reset)) {
1799 		/* Reset vwidx_cached_flag[] when espi_reset# asserted. */
1800 		espi_it8xxx2_reset_vwidx_cache(ESPI_IT8XXX2_SOC_DEV);
1801 	}
1802 
1803 	evt.evt_data = espi_reset;
1804 	espi_send_callbacks(&data->callbacks, ESPI_IT8XXX2_SOC_DEV, evt);
1805 
1806 	LOG_INF("eSPI reset %sasserted", espi_reset ? "de" : "");
1807 }
1808 
1809 /* eSPI reset# is enabled on GPD2 */
1810 #define ESPI_IT8XXX2_ESPI_RESET_PORT DEVICE_DT_GET(DT_NODELABEL(gpiod))
1811 #define ESPI_IT8XXX2_ESPI_RESET_PIN  2
espi_it8xxx2_enable_reset(void)1812 static void espi_it8xxx2_enable_reset(void)
1813 {
1814 	struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;
1815 	static struct gpio_callback espi_reset_cb;
1816 
1817 	/* eSPI reset is enabled on GPD2 */
1818 	gpio_regs->GPIO_GCR =
1819 		(gpio_regs->GPIO_GCR & ~IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK) |
1820 		(IT8XXX2_GPIO_GCR_ESPI_RST_D2 << IT8XXX2_GPIO_GCR_ESPI_RST_POS);
1821 	/* enable eSPI reset isr */
1822 	gpio_init_callback(&espi_reset_cb, espi_it8xxx2_espi_reset_isr,
1823 				BIT(ESPI_IT8XXX2_ESPI_RESET_PIN));
1824 	gpio_add_callback(ESPI_IT8XXX2_ESPI_RESET_PORT, &espi_reset_cb);
1825 	gpio_pin_interrupt_configure(ESPI_IT8XXX2_ESPI_RESET_PORT,
1826 					ESPI_IT8XXX2_ESPI_RESET_PIN,
1827 					GPIO_INT_MODE_EDGE | GPIO_INT_TRIG_BOTH);
1828 }
1829 
1830 static struct espi_it8xxx2_data espi_it8xxx2_data_0;
1831 static const struct espi_it8xxx2_config espi_it8xxx2_config_0 = {
1832 	.base_espi_slave = DT_INST_REG_ADDR_BY_IDX(0, 0),
1833 	.base_espi_vw = DT_INST_REG_ADDR_BY_IDX(0, 1),
1834 	.base_espi_queue0 = DT_INST_REG_ADDR_BY_IDX(0, 2),
1835 	.base_espi_queue1 = DT_INST_REG_ADDR_BY_IDX(0, 3),
1836 	.base_ec2i = DT_INST_REG_ADDR_BY_IDX(0, 4),
1837 	.base_kbc = DT_INST_REG_ADDR_BY_IDX(0, 5),
1838 	.base_pmc = DT_INST_REG_ADDR_BY_IDX(0, 6),
1839 	.base_smfi = DT_INST_REG_ADDR_BY_IDX(0, 7),
1840 	.wuc = IT8XXX2_DT_WUC_ITEMS_FUNC(0, 0),
1841 };
1842 
1843 DEVICE_DT_INST_DEFINE(0, &espi_it8xxx2_init, NULL,
1844 		    &espi_it8xxx2_data_0, &espi_it8xxx2_config_0,
1845 		    PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1846 		    &espi_it8xxx2_driver_api);
1847 
espi_it8xxx2_init(const struct device * dev)1848 static int espi_it8xxx2_init(const struct device *dev)
1849 {
1850 	const struct espi_it8xxx2_config *const config = dev->config;
1851 	struct espi_vw_regs *const vw_reg =
1852 		(struct espi_vw_regs *)config->base_espi_vw;
1853 	struct espi_slave_regs *const slave_reg =
1854 		(struct espi_slave_regs *)config->base_espi_slave;
1855 	struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
1856 
1857 	/* configure VCC detector */
1858 	gctrl->GCTRL_RSTS = (gctrl->GCTRL_RSTS &
1859 			~(IT8XXX2_GCTRL_VCCDO_MASK | IT8XXX2_GCTRL_HGRST)) |
1860 			(IT8XXX2_GCTRL_VCCDO_VCC_ON | IT8XXX2_GCTRL_GRST);
1861 
1862 	/* enable PNPCFG devices */
1863 	pnpcfg_it8xxx2_init(dev);
1864 
1865 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
1866 	/* enable kbc port (60h/64h) */
1867 	kbc_it8xxx2_init(dev);
1868 #endif
1869 #ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
1870 	/* enable pmc1 for ACPI port (62h/66h) */
1871 	pmc1_it8xxx2_init(dev);
1872 #endif
1873 #ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
1874 	/* Accept Port 80h Cycle */
1875 	port80_it8xxx2_init(dev);
1876 #endif
1877 #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
1878 	defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
1879 	smfi_it8xxx2_init(dev);
1880 #endif
1881 #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
1882 	/* enable pmc2 for host command port */
1883 	pmc2_it8xxx2_init(dev);
1884 #endif
1885 
1886 	/* Reset vwidx_cached_flag[] at initialization */
1887 	espi_it8xxx2_reset_vwidx_cache(dev);
1888 
1889 	/* Enable espi vw interrupt */
1890 	vw_reg->VWCTRL0 |= IT8XXX2_ESPI_VW_INTERRUPT_ENABLE;
1891 	IRQ_CONNECT(IT8XXX2_ESPI_VW_IRQ, 0, espi_it8xxx2_vw_isr,
1892 			DEVICE_DT_INST_GET(0), 0);
1893 	irq_enable(IT8XXX2_ESPI_VW_IRQ);
1894 
1895 	/* Reset PLTRST# virtual wire signal during eSPI reset */
1896 	vw_reg->VWCTRL2 |= IT8XXX2_ESPI_VW_RESET_PLTRST;
1897 
1898 #ifdef CONFIG_ESPI_OOB_CHANNEL
1899 	espi_it8xxx2_oob_init(dev);
1900 #endif
1901 
1902 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1903 	espi_it8xxx2_flash_init(dev);
1904 #endif
1905 
1906 	/* Enable espi interrupt */
1907 	slave_reg->ESGCTRL1 |= IT8XXX2_ESPI_INTERRUPT_ENABLE;
1908 	IRQ_CONNECT(IT8XXX2_ESPI_IRQ, 0, espi_it8xxx2_isr,
1909 			DEVICE_DT_INST_GET(0), 0);
1910 	irq_enable(IT8XXX2_ESPI_IRQ);
1911 
1912 	/* enable interrupt and reset from eSPI_reset# */
1913 	espi_it8xxx2_enable_reset();
1914 
1915 	/*
1916 	 * Enable eSPI to WUC.
1917 	 * If an eSPI transaction is accepted, WU42 interrupt will be asserted.
1918 	 */
1919 	slave_reg->ESGCTRL2 |= IT8XXX2_ESPI_TO_WUC_ENABLE;
1920 
1921 	/* Enable WU42 of WUI */
1922 	it8xxx2_wuc_clear_status(config->wuc.wucs, config->wuc.mask);
1923 	it8xxx2_wuc_enable(config->wuc.wucs, config->wuc.mask);
1924 	/*
1925 	 * Only register isr here, the interrupt only need to be enabled
1926 	 * before CPU and RAM clocks gated in the idle function.
1927 	 */
1928 	IRQ_CONNECT(IT8XXX2_TRANS_IRQ, 0, espi_it8xxx2_trans_isr,
1929 			DEVICE_DT_INST_GET(0), 0);
1930 
1931 	return 0;
1932 }
1933