pll_source (reference) in projects: Zephyr-Core-3.5.0

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Searched refs:pll_source (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.5.0/drivers/clock_control/
D	clock_stm32f0_f3.c	48 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local 80 pll_source = LL_RCC_PLLSOURCE_HSE; in config_pll_sysclock() 82 pll_source = LL_RCC_PLLSOURCE_HSI; in config_pll_sysclock() 87 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div); in config_pll_sysclock() 91 pll_source = LL_RCC_PLLSOURCE_HSE \| pll_div; in config_pll_sysclock() 93 pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2; in config_pll_sysclock() 98 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul); in config_pll_sysclock()
D	clock_stm32f1.c	`41 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local 93 pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2; in config_pll_sysclock() 95 pll_source = LL_RCC_PLLSOURCE_HSE \| pll_div; in config_pll_sysclock() 98 pll_source = LL_RCC_PLLSOURCE_PLL2 \| pll_div; in config_pll_sysclock() 104 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul); in config_pll_sysclock()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
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babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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cmsis-nn-3.6.0-3.5.0
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