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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h19 #define MCHP_XEC_ECIA(g, gb, na, nd) \ argument
21 (((nd) & 0xff) << 24))
/Zephyr-Core-3.5.0/tests/cmake/zephyr_get/
DCMakeLists.txt135 IMAGE zephyr_get_2nd "sysbuild.2nd"
149 IMAGE zephyr_get_2nd "sysbuild.2nd"
169 IMAGE zephyr_get_2nd "sysbuild.2nd"
220 IMAGE zephyr_get_2nd "sysbuild.2nd"
233 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main"
246 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;cmake cache;environment;local"
255 IMAGE zephyr_get_2nd "sysbuild.2nd;cmake cache;environment"
267 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;environment"
364 IMAGE zephyr_get_2nd "sysbuild.2nd"
371 IMAGE zephyr_get_2nd "sysbuild.2nd"
[all …]
Dsysbuild.cmake6 foreach(suffix "2nd" "3rd")
/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
Dlinker.ld13 /* Using mcuboot as ESP32C3 2nd stage bootloader */
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32/
Dlinker.ld13 /* Using mcuboot as ESP32 2nd stage bootloader */
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/
Dlinker.ld13 /* Using mcuboot as ESP32S2 2nd stage bootloader */
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s3/
Dlinker.ld13 /* Using mcuboot as ESP32S3 2nd stage bootloader */
/Zephyr-Core-3.5.0/arch/arc/core/
Dreset.S95 bz.nd done_icache_invalidate
108 bz.nd done_dcache_invalidate
/Zephyr-Core-3.5.0/cmake/sca/sparse/
Dsparse.template8 # argument to be passed to sparse is 2nd argument after `--`.
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
DKconfig.dw18 Designware Interrupt Controller can be used as a 2nd level interrupt
DKconfig.multilevel51 where storage for 2nd level interrupt ISRs begins. This is
/Zephyr-Core-3.5.0/boards/arm/mimx8mm_phyboard_polis/
Dmimx8mm_phyboard_polis.dts75 /* UART of the M4 Core (2nd tty on Debug USB connector) */
/Zephyr-Core-3.5.0/samples/drivers/espi/
DREADME.rst48 2nd phase completed
/Zephyr-Core-3.5.0/drivers/serial/
DKconfig.native_posix70 The 2nd UART will not be affected by this option.
/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_franzininho/doc/
Dindex.rst60 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/riscv/stamp_c3/doc/
Dindex.rst62 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/odroid_go/doc/
Dindex.rst104 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/riscv/xiao_esp32c3/doc/
Dindex.rst86 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/heltec_wifi_lora32_v2/doc/
Dindex.rst48 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/xiao_esp32s3/doc/
Dindex.rst102 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_saola/doc/
Dindex.rst94 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/riscv/esp32c3_devkitm/doc/
Dindex.rst98 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/riscv/esp32c3_luatos_core/doc/
Dindex.rst116 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/m5stickc_plus/doc/
Dindex.rst93 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
/Zephyr-Core-3.5.0/boards/xtensa/olimex_esp32_evb/doc/
Dindex.rst114 The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.

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