| /Zephyr-Core-3.5.0/scripts/kconfig/ |
| D | hardened.csv | 1 BOOT_BANNER,n
4 BT_CONN_DISABLE_SECURITY,n
5 BT_DEBUG_KEYS,n
6 BT_DEBUG_SMP,n
7 BT_FIXED_PASSKEY,n
8 BT_LOG_SNIFFER_INFO,n
9 BT_OOB_DATA_FIXED,n
11 BT_STORE_DEBUG_KEYS,n
12 BT_TESTING,n
13 BT_USE_DEBUG_KEYS,n
[all …]
|
| /Zephyr-Core-3.5.0/include/zephyr/math/ |
| D | ilog2.h | 39 #define ilog2_compile_time_const_u32(n) \ argument
41 ((n) < 2) ? 0 : \
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
49 (((n) & BIT(24)) == BIT(24)) ? 24 : \
[all …]
|
| /Zephyr-Core-3.5.0/samples/bluetooth/peripheral_hr/ |
| D | prj_minimal.conf | 5 CONFIG_BT_DIS_PNP=n
12 CONFIG_I2C=n
13 CONFIG_WATCHDOG=n
14 CONFIG_PINCTRL=n
15 CONFIG_SPI=n
16 CONFIG_GPIO=n
17 CONFIG_SERIAL=n
20 CONFIG_PM=n
23 CONFIG_DYNAMIC_INTERRUPTS=n
24 CONFIG_IRQ_OFFLOAD=n
[all …]
|
| /Zephyr-Core-3.5.0/samples/net/sockets/big_http_download/src/ |
| D | isrgrootx1.pem | 1 "-----BEGIN CERTIFICATE-----\n"
2 "MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw\n"
3 "TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh\n"
4 "cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4\n"
5 "WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu\n"
6 "ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY\n"
7 "MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc\n"
8 "h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+\n"
9 "0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U\n"
10 "A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW\n"
[all …]
|
| D | DigiCertGlobalRootG2.crt.pem | 1 "-----BEGIN CERTIFICATE-----\n"
2 "MIIDjjCCAnagAwIBAgIQAzrx5qcRqaC7KGSxHQn65TANBgkqhkiG9w0BAQsFADBh\n"
3 "MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n"
4 "d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBH\n"
5 "MjAeFw0xMzA4MDExMjAwMDBaFw0zODAxMTUxMjAwMDBaMGExCzAJBgNVBAYTAlVT\n"
6 "MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n"
7 "b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IEcyMIIBIjANBgkqhkiG\n"
8 "9w0BAQEFAAOCAQ8AMIIBCgKCAQEAuzfNNNx7a8myaJCtSnX/RrohCgiN9RlUyfuI\n"
9 "2/Ou8jqJkTx65qsGGmvPrC3oXgkkRLpimn7Wo6h+4FR1IAWsULecYxpsMNzaHxmx\n"
10 "1x7e/dfgy5SDN67sH0NO3Xss0r0upS/kqbitOtSZpLYl6ZtrAGCSYP9PIUkY92eQ\n"
[all …]
|
| /Zephyr-Core-3.5.0/tests/bluetooth/init/ |
| D | prj_ctlr_tiny.conf | 5 CONFIG_BT_CTLR_CONN_PARAM_REQ=n
6 CONFIG_BT_CTLR_EXT_REJ_IND=n
7 CONFIG_BT_CTLR_PER_INIT_FEAT_XCHG=n
8 CONFIG_BT_CTLR_LE_PING=n
9 CONFIG_BT_CTLR_PRIVACY=n
10 CONFIG_BT_CTLR_EXT_SCAN_FP=n
11 CONFIG_BT_DATA_LEN_UPDATE=n
12 CONFIG_BT_PHY_UPDATE=n
13 CONFIG_BT_CTLR_CHAN_SEL_2=n
14 CONFIG_BT_CTLR_MIN_USED_CHAN=n
[all …]
|
| D | prj_ctlr_4_0.conf | 5 CONFIG_BT_CTLR_CONN_PARAM_REQ=n
6 CONFIG_BT_CTLR_LE_PING=n
7 CONFIG_BT_CTLR_PRIVACY=n
8 CONFIG_BT_CTLR_EXT_SCAN_FP=n
9 CONFIG_BT_DATA_LEN_UPDATE=n
10 CONFIG_BT_PHY_UPDATE=n
11 CONFIG_BT_CTLR_CHAN_SEL_2=n
12 CONFIG_BT_CTLR_MIN_USED_CHAN=n
13 CONFIG_BT_CTLR_ADV_EXT=n
20 CONFIG_BT_CTLR_RADIO_ENABLE_FAST=n
[all …]
|
| D | prj_ctlr_4_0_dbg.conf | 5 CONFIG_BT_CTLR_CONN_PARAM_REQ=n
6 CONFIG_BT_CTLR_LE_PING=n
8 CONFIG_BT_CTLR_EXT_SCAN_FP=n
9 CONFIG_BT_DATA_LEN_UPDATE=n
10 CONFIG_BT_PHY_UPDATE=n
11 CONFIG_BT_CTLR_CHAN_SEL_2=n
12 CONFIG_BT_CTLR_MIN_USED_CHAN=n
13 CONFIG_BT_CTLR_ADV_EXT=n
22 CONFIG_BT_CTLR_RADIO_ENABLE_FAST=n
24 CONFIG_BT_CTLR_CONN_RSSI=n
[all …]
|
| /Zephyr-Core-3.5.0/samples/basic/minimal/ |
| D | common.conf | 2 CONFIG_I2C=n
3 CONFIG_WATCHDOG=n
4 CONFIG_GPIO=n
5 CONFIG_PINCTRL=n
6 CONFIG_SPI=n
7 CONFIG_SERIAL=n
8 CONFIG_FLASH=n
11 CONFIG_PM=n
14 CONFIG_DYNAMIC_INTERRUPTS=n
15 CONFIG_IRQ_OFFLOAD=n
[all …]
|
| D | common-runtime.conf | 2 CONFIG_I2C=n
3 CONFIG_WATCHDOG=n
4 CONFIG_GPIO=n
5 CONFIG_PINCTRL=n
6 CONFIG_SPI=n
7 CONFIG_FLASH=n
8 CONFIG_UART_USE_RUNTIME_CONFIGURE=n
9 CONFIG_UART_INTERRUPT_DRIVEN=n
15 CONFIG_CBPRINTF_LIBC_SUBSTS=n
18 CONFIG_FPU=n
|
| /Zephyr-Core-3.5.0/drivers/memc/ |
| D | memc_nxp_s32_qspi.c | 79 #define QSPI_DATA_CFG(n) \ argument
82 DT_INST_STRING_UPPER_TOKEN(n, data_rate)), \
83 .dataAlign = COND_CODE_1(DT_INST_PROP(n, hold_time_2x), \
88 #define QSPI_ADDR_CFG(n) \ argument
90 .columnAddr = DT_INST_PROP_OR(n, column_space, 0), \
91 .wordAddresable = DT_INST_PROP(n, word_addressable), \
94 #define QSPI_BYTES_SWAP_ADDR(n) \ argument
96 (.byteSwap = DT_INST_PROP(n, byte_swapping),))
98 #define QSPI_SAMPLE_DELAY(n) \ argument
99 COND_CODE_1(DT_INST_PROP(n, sample_delay_half_cycle), \
[all …]
|
| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_nct38xx.h | 19 #define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8)) argument
20 #define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8)) argument
21 #define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8)) argument
22 #define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8)) argument
23 #define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8)) argument
24 #define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8)) argument
25 #define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8)) argument
26 #define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8)) argument
28 #define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n)) argument
|
| /Zephyr-Core-3.5.0/samples/net/cloud/mqtt_azure/src/ |
| D | digicert.cer | 1 "-----BEGIN CERTIFICATE-----\r\n"
2 "MIIDdzCCAl+gAwIBAgIEAgAAuTANBgkqhkiG9w0BAQUFADBaMQswCQYDVQQGEwJJ\r\n"
3 "RTESMBAGA1UEChMJQmFsdGltb3JlMRMwEQYDVQQLEwpDeWJlclRydXN0MSIwIAYD\r\n"
4 "VQQDExlCYWx0aW1vcmUgQ3liZXJUcnVzdCBSb290MB4XDTAwMDUxMjE4NDYwMFoX\r\n"
5 "DTI1MDUxMjIzNTkwMFowWjELMAkGA1UEBhMCSUUxEjAQBgNVBAoTCUJhbHRpbW9y\r\n"
6 "ZTETMBEGA1UECxMKQ3liZXJUcnVzdDEiMCAGA1UEAxMZQmFsdGltb3JlIEN5YmVy\r\n"
7 "VHJ1c3QgUm9vdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKMEuyKr\r\n"
8 "mD1X6CZymrV51Cni4eiVgLGw41uOKymaZN+hXe2wCQVt2yguzmKiYv60iNoS6zjr\r\n"
9 "IZ3AQSsBUnuId9Mcj8e6uYi1agnnc+gRQKfRzMpijS3ljwumUNKoUMMo6vWrJYeK\r\n"
10 "mpYcqWe4PwzV9/lSEy/CG9VwcPCPwBLKBsua4dnKM3p31vjsufFoREJIE9LAwqSu\r\n"
[all …]
|
| /Zephyr-Core-3.5.0/drivers/mbox/ |
| D | mbox_nxp_s32_mru.c | 22 #define MRU_NODE(n) DT_NODELABEL(mru##n) argument
23 #define MRU_BASE(n) ((RTU_MRU_Type *)DT_REG_ADDR(MRU_NODE(n))) argument
24 #define MRU_RX_CHANNELS(n) DT_PROP_OR(MRU_NODE(n), rx_channels, 0) argument
25 #define MRU_MBOX_ADDR(n, ch, mb) \ argument
26 (DT_REG_ADDR(MRU_NODE(n)) + ((ch + 1) * MRU_CHANNEL_OFFSET) + (MRU_MBOX_SIZE * mb))
34 #define MRU_ISR_FUNC(n) \ argument
35 _CONCAT7(Mru_Ip_RTU, CONFIG_NXP_S32_RTU_INDEX, _MRU, n, _Int, \
36 MRU_INT_GROUP(DT_IRQN(MRU_NODE(n))), _IRQHandler)
189 #define MRU_ISR_FUNC_DECLARE(n) extern void MRU_ISR_FUNC(n)(void) argument
191 #define MRU_INIT_IRQ_FUNC(n) \ argument
[all …]
|
| /Zephyr-Core-3.5.0/lib/libc/minimal/source/string/ |
| D | string.c | 42 char *strncpy(char *ZRESTRICT d, const char *ZRESTRICT s, size_t n) in strncpy() argument
46 while ((n > 0) && *s != '\0') { in strncpy()
50 n--; in strncpy()
53 while (n > 0) { in strncpy()
56 n--; in strncpy()
109 size_t n = 0; in strlen() local
113 n++; in strlen()
116 return n; in strlen()
143 int strncmp(const char *s1, const char *s2, size_t n) in strncmp() argument
145 while ((n > 0) && (*s1 == *s2) && (*s1 != '\0')) { in strncmp()
[all …]
|
| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 25 #define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) argument
26 #define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) argument
27 #define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) argument
28 #define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) argument
29 #define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) argument
30 #define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) argument
31 #define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) argument
32 #define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) argument
33 #define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) argument
|
| D | intc_eirq_nxp_s32.c | 127 #define EIRQ_NXP_S32_NODE(n) DT_NODELABEL(eirq##n) argument
129 #define EIRQ_NXP_S32_CALLBACK(line, n) \ argument
130 void nxp_s32_icu_##n##_eirq_line_##line##_callback(void) \
132 const struct device *dev = DEVICE_DT_GET(EIRQ_NXP_S32_NODE(n)); \
137 #define EIRQ_NXP_S32_CHANNEL_CONFIG(idx, n) \ argument
140 .digFilterEn = DT_PROP_OR(DT_CHILD(EIRQ_NXP_S32_NODE(n), line_##idx), \
142 .maxFilterCnt = DT_PROP_OR(DT_CHILD(EIRQ_NXP_S32_NODE(n), line_##idx), \
147 .Siul2ChannelNotification = nxp_s32_icu_##n##_eirq_line_##idx##_callback, \
151 #define EIRQ_NXP_S32_CHANNELS_CONFIG(n) \ argument
152 static const Siul2_Icu_Ip_ChannelConfigType eirq_##n##_channel_nxp_s32_cfg[] = { \
[all …]
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| D | intc_wkpu_nxp_s32.c | 124 #define WKPU_NXP_S32_CALLBACK(line, n) \ argument
125 void nxp_s32_wkpu_##n##wkpu_line_##line##_callback(void) \
127 const struct device *dev = DEVICE_DT_INST_GET(n); \
132 #define WKPU_NXP_S32_CHANNEL_CONFIG(idx, n) \ argument
135 .filterEn = DT_INST_PROP_OR(DT_INST_CHILD(n, line_##idx), filter_enable, 0), \
137 .WkpuChannelNotification = nxp_s32_wkpu_##n##wkpu_line_##idx##_callback, \
142 #define WKPU_NXP_S32_CHANNELS_CONFIG(n) \ argument
143 static const Wkpu_Ip_ChannelConfigType wkpu_##n##_channel_nxp_s32_cfg[] = { \
144 LISTIFY(NXP_S32_NUM_CHANNELS_DEBRACKET, WKPU_NXP_S32_CHANNEL_CONFIG, (,), n) \
147 #define WKPU_NXP_S32_INSTANCE_CONFIG(n) \ argument
[all …]
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| /Zephyr-Core-3.5.0/drivers/misc/nxp_s32_emios/ |
| D | nxp_s32_emios.c | 46 #define NXP_S32_EMIOS_INSTANCE_CHECK(idx, n) \ argument
47 ((DT_INST_REG_ADDR(n) == IP_EMIOS_##idx##_BASE) ? idx : 0)
49 #define NXP_S32_EMIOS_GET_INSTANCE(n) \ argument
50 LISTIFY(__DEBRACKET eMIOS_INSTANCE_COUNT, NXP_S32_EMIOS_INSTANCE_CHECK, (|), n)
52 #define NXP_S32_EMIOS_GENERATE_GLOBAL_CONFIG(n) \ argument
53 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, clock_divider), \
56 const Emios_Ip_GlobalConfigType nxp_s32_emios_##n##_global_config = { \
58 .clkDivVal = DT_INST_PROP(n, clock_divider) - 1U, \
77 #define NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n) \ argument
78 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
[all …]
|
| /Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/ |
| D | atmel_sam0_dt.h | 18 #define MCLK_MASK_DT_INT_REG_ADDR(n) \ argument
19 (DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
20 DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
25 #define ATMEL_SAM0_DT_INST_DMA_CELL(n, name, cell) \ argument
26 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
27 (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
29 #define ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, name) \ argument
30 ATMEL_SAM0_DT_INST_DMA_CELL(n, name, trigsrc)
31 #define ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, name) \ argument
32 ATMEL_SAM0_DT_INST_DMA_CELL(n, name, channel)
[all …]
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| /Zephyr-Core-3.5.0/samples/modules/tflite-micro/hello_world/train/ |
| D | train_hello_world_model.ipynb | 23 "# Train a Simple TensorFlow Lite for Microcontrollers model\n",
24 "\n",
25 …kB model using TensorFlow and converting it for use with TensorFlow Lite for Microcontrollers. \n",
26 "\n",
27 …e) function. This will result in a model that can take a value, `x`, and predict its sine, `y`.\n",
28 "\n",
29 …nsorFlow Lite for MicroControllers](https://www.tensorflow.org/lite/microcontrollers/overview).\n",
30 "\n",
31 "<table class=\"tfo-notebook-buttons\" align=\"left\">\n",
32 " <td>\n",
[all …]
|
| /Zephyr-Core-3.5.0/drivers/display/ |
| D | display_ili9341.h | 84 #define ILI9341_REGS_INIT(n) \ argument
85 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), gamset) == ILI9341_GAMSET_LEN, \
87 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ifmode) == ILI9341_IFMODE_LEN, \
89 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), frmctr1) == ILI9341_FRMCTR1_LEN, \
91 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), disctrl) == ILI9341_DISCTRL_LEN, \
93 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl1) == ILI9341_PWCTRL1_LEN, \
95 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl2) == ILI9341_PWCTRL2_LEN, \
97 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl1) == ILI9341_VMCTRL1_LEN, \
99 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl2) == ILI9341_VMCTRL2_LEN, \
101 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pgamctrl) == ILI9341_PGAMCTRL_LEN, \
[all …]
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| /Zephyr-Core-3.5.0/drivers/ethernet/ |
| D | eth_nxp_s32_netc_vsi.c | 29 #define VSI_NODE(n) DT_NODELABEL(enetc_vsi##n) argument
85 #define NETC_VSI_INSTANCE_DEFINE(n) \ argument
86 NETC_GENERATE_MAC_ADDRESS(VSI_NODE(n), n) \
88 static void nxp_s32_eth##n##_rx_callback(const uint8_t unused, const uint8_t ring) \
90 const struct device *dev = DEVICE_DT_GET(VSI_NODE(n)); \
99 static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
100 Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
103 nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
105 NETC_RX_RING(n, TX_RING_IDX, CONFIG_ETH_NXP_S32_RX_RING_LEN, \
107 NETC_TX_RING(n, RX_RING_IDX, CONFIG_ETH_NXP_S32_TX_RING_LEN, \
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/cypress/common/ |
| D | cypress_psoc6_dt.h | 65 #define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) \ argument
66 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupt_parent),\
67 (CY_PSOC6_IRQ_CONFIG(n, isr)))
68 #define CY_PSOC6_NVIC_MUX_IRQN(n) DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\ argument
71 #define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_IRQ(DT_INST_PHANDLE_BY_IDX(n,\ argument
81 #define CY_PSOC6_NVIC_MUX_MAP(n) Cy_SysInt_SetInterruptSource( \ argument
82 DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\
84 DT_INST_PROP_BY_IDX(n, interrupts, 0))
91 #define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) CY_PSOC6_IRQ_CONFIG(n, isr) argument
92 #define CY_PSOC6_NVIC_MUX_IRQN(n) DT_INST_IRQN(n) argument
[all …]
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| /Zephyr-Core-3.5.0/drivers/disk/ |
| D | ramdisk.c | 127 #define RAMDISK_DEVICE_SIZE(n) \ argument
128 (DT_INST_PROP(n, sector_size) * DT_INST_PROP(n, sector_count))
130 #define RAMDISK_DEVICE_CONFIG_DEFINE_MEMREG(n) \ argument
131 BUILD_ASSERT(RAMDISK_DEVICE_SIZE(n) <= \
132 DT_REG_SIZE(DT_INST_PHANDLE(n, ram_region)), \
135 static struct ram_disk_config disk_config_##n = { \
136 .sector_size = DT_INST_PROP(n, sector_size), \
137 .sector_count = DT_INST_PROP(n, sector_count), \
138 .size = RAMDISK_DEVICE_SIZE(n), \
139 .buf = UINT_TO_POINTER(DT_REG_ADDR(DT_INST_PHANDLE(n, ram_region))), \
[all …]
|
