Searched refs:mod_clk (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_rcar.c | 57 struct rcar_cpg_clk mod_clk; member
231 ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->mod_clk); in pwm_rcar_init()
258 .mod_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
259 .mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
|
| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | rcar_cmt_timer.c | 29 static struct rcar_cpg_clk mod_clk = { variable
103 ret = clock_control_on(clk, (clock_control_subsys_t)&mod_clk); in sys_clock_driver_init()
|
| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_rcar.c | 33 struct rcar_cpg_clk mod_clk; member
248 (clock_control_subsys_t) &config->mod_clk); in gpio_rcar_init()
290 .mod_clk.module = \
292 .mod_clk.domain = \
|
| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_rcar.c | 28 struct rcar_cpg_clk mod_clk; member
329 (clock_control_subsys_t)&config->mod_clk); in i2c_rcar_init()
360 .mod_clk.module = \
362 .mod_clk.domain = \
|
| /Zephyr-Core-3.5.0/drivers/audio/ |
| D | tlv320dac310x.c | 260 int dac_clk, mod_clk; in codec_configure_clocks() local
297 mod_clk = i2s->frame_clk_freq * osr; in codec_configure_clocks()
300 mdac = dac_clk / mod_clk; in codec_configure_clocks()
303 if ((mdac * mod_clk) == dac_clk) { in codec_configure_clocks()
317 dac_clk, mod_clk); in codec_configure_clocks()
|
| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_rcar.c | 22 struct rcar_cpg_clk mod_clk; member
279 (clock_control_subsys_t)&config->mod_clk); in uart_rcar_init()
526 .mod_clk.module = \
528 .mod_clk.domain = \
|
| /Zephyr-Core-3.5.0/drivers/can/ |
| D | can_rcar.c | 173 struct rcar_cpg_clk mod_clk; member
1029 (clock_control_subsys_t)&config->mod_clk); in can_rcar_init()
1035 (clock_control_subsys_t)&config->mod_clk); in can_rcar_init()
1196 .mod_clk.module = \
1198 .mod_clk.domain = \
|
