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Searched refs:mm_reg_t (Results 1 – 25 of 54) sorted by relevance

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/Zephyr-Core-3.5.0/include/zephyr/arch/nios2/
Dasm_inline_gcc.h24 static ALWAYS_INLINE void sys_write32(uint32_t data, mm_reg_t addr) in sys_write32()
29 static ALWAYS_INLINE uint32_t sys_read32(mm_reg_t addr) in sys_read32()
34 static ALWAYS_INLINE void sys_write8(uint8_t data, mm_reg_t addr) in sys_write8()
39 static ALWAYS_INLINE uint8_t sys_read8(mm_reg_t addr) in sys_read8()
44 static ALWAYS_INLINE void sys_write16(uint16_t data, mm_reg_t addr) in sys_write16()
49 static ALWAYS_INLINE uint16_t sys_read16(mm_reg_t addr) in sys_read16()
Dnios2.h166 (mm_reg_t)z_nios2_get_register_address(base, regnum)); in _nios2_reg_write()
171 return sys_read32((mm_reg_t)z_nios2_get_register_address(base, regnum)); in _nios2_reg_read()
/Zephyr-Core-3.5.0/include/zephyr/sys/
Ddevice_mmio.h96 static inline void device_map(mm_reg_t *virt_addr, uintptr_t phys_addr, in device_map()
121 mm_reg_t addr;
126 .addr = (mm_reg_t)DT_REG_ADDR_U64(node_id) \
131 .addr = (mm_reg_t)DT_REG_ADDR_BY_NAME_U64(node_id, name) \
176 #define DEVICE_MMIO_RAM mm_reg_t _mmio
192 #define DEVICE_MMIO_RAM_PTR(device) (mm_reg_t *)((device)->data)
349 #define DEVICE_MMIO_NAMED_RAM(name) mm_reg_t name
587 mm_reg_t Z_TOPLEVEL_RAM_NAME(name); \
614 extern mm_reg_t Z_TOPLEVEL_RAM_NAME(name); \
638 static mm_reg_t Z_TOPLEVEL_RAM_NAME(name); \
[all …]
Dsys_io.h20 typedef uintptr_t mm_reg_t; typedef
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_agilex5_ll.c17 mm_reg_t base_addr;
18 mm_reg_t mainpll_addr;
19 mm_reg_t peripll_addr;
20 mm_reg_t ctl_addr;
27 void clock_agilex5_ll_init(mm_reg_t base_addr) in clock_agilex5_ll_init()
Dclock_control_agilex5_ll.h113 void clock_agilex5_ll_init(mm_reg_t base_addr);
/Zephyr-Core-3.5.0/include/zephyr/arch/x86/
Darch.h95 static ALWAYS_INLINE void sys_write8(uint8_t data, mm_reg_t addr) in sys_write8()
103 static ALWAYS_INLINE uint8_t sys_read8(mm_reg_t addr) in sys_read8()
115 static ALWAYS_INLINE void sys_write16(uint16_t data, mm_reg_t addr) in sys_write16()
123 static ALWAYS_INLINE uint16_t sys_read16(mm_reg_t addr) in sys_read16()
135 static ALWAYS_INLINE void sys_write32(uint32_t data, mm_reg_t addr) in sys_write32()
143 static ALWAYS_INLINE uint32_t sys_read32(mm_reg_t addr) in sys_read32()
/Zephyr-Core-3.5.0/tests/kernel/device/src/
Dmmio.c65 mm_reg_t regs; in ZTEST()
162 mm_reg_t regs_corge, regs_grault; in ZTEST()
223 mm_reg_t regs_foo3, regs_foo4; in ZTEST()
265 mm_reg_t regs = 0; in ZTEST()
/Zephyr-Core-3.5.0/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c62 static mm_reg_t regs(const struct device *dev) in regs()
87 mm_reg_t addr = regs(dev); in tgpio_intel_pin_disable()
105 mm_reg_t addr = regs(dev); in tgpio_intel_periodic_output()
145 mm_reg_t addr = regs(dev); in tgpio_intel_config_external_timestamp()
/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dloapic.h87 mm_reg_t base; in x86_read_xapic()
131 mm_reg_t base; in x86_write_xapic()
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_xlnx_axi_timer.c43 mm_reg_t base;
49 mm_reg_t offset) in xlnx_axi_timer_read32()
58 mm_reg_t offset) in xlnx_axi_timer_write32()
/Zephyr-Core-3.5.0/include/zephyr/arch/x86/intel64/
Darch.h25 static ALWAYS_INLINE void sys_write64(uint64_t data, mm_reg_t addr) in sys_write64()
34 static ALWAYS_INLINE uint64_t sys_read64(mm_reg_t addr) in sys_read64()
/Zephyr-Core-3.5.0/drivers/can/
Dcan_esp32_twai.c69 mm_reg_t base;
84 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_read_reg()
93 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_write_reg()
107 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_write_reg32()
/Zephyr-Core-3.5.0/arch/x86/core/
Dearly_serial.c26 static mm_reg_t mmio;
34 static mm_reg_t mmio;
/Zephyr-Core-3.5.0/drivers/pcie/host/
Dmsi.c210 sys_write32(map, (mm_reg_t) &vectors[i].msix_vector->msg_addr); in enable_msix()
211 sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->msg_up_addr); in enable_msix()
212 sys_write32(mdr, (mm_reg_t) &vectors[i].msix_vector->msg_data); in enable_msix()
213 sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->vector_ctrl); in enable_msix()
/Zephyr-Core-3.5.0/drivers/disk/nvme/
Dnvme_helpers.h504 sys_read32((mm_reg_t)b_a + nvme_mmio_offsetof(reg))
507 sys_write32(val, (mm_reg_t)b_a + nvme_mmio_offsetof(reg))
512 (mm_reg_t)b_a + nvme_mmio_offsetof(reg)); \
514 (mm_reg_t)b_a + nvme_mmio_offsetof(reg) + 4); \
Dnvme_controller.c27 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_wait_for_ready()
59 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_disable()
96 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_enable()
140 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_setup_admin_queues()
256 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_gather_info()
/Zephyr-Core-3.5.0/drivers/mm/
Dmm_drv_intel_adsp.h36 ((mm_reg_t)DEVICE_MMIO_TOPLEVEL_GET(tlb_regs))
/Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/
Dcontroller.h141 uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg);
156 void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_neorv32.c30 mm_reg_t input;
31 mm_reg_t output;
/Zephyr-Core-3.5.0/subsys/shell/modules/
Ddevmem_service.c43 mm_reg_t addr; in memory_dump()
48 device_map((mm_reg_t *)&addr, phys_addr, size, K_MEM_CACHE_NONE); in memory_dump()
323 device_map((mm_reg_t *)&addr, phys_addr, 0x100, K_MEM_CACHE_NONE); in cmd_devmem()
/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_xlnx_zynq.c26 static mm_reg_t base = DT_INST_REG_ADDR(0);
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_xlnx_axi_timer.c47 mm_reg_t base;
59 mm_reg_t offset) in xlnx_axi_timer_read32()
68 mm_reg_t offset) in xlnx_axi_timer_write32()
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxxs/
Dsoc.c110 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxx/
Dsoc.c110 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in z_arm_platform_init()

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