1 /* 2 * Copyright (c) 2019, MADMACHINE LIMITED 3 * 4 * refer to hal_nxp board file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef __FLEXSPI_NOR_CONFIG__ 10 #define __FLEXSPI_NOR_CONFIG__ 11 12 #include <zephyr/types.h> 13 #include "fsl_common.h" 14 15 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) 16 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) 17 #define FLEXSPI_CFG_BLK_SIZE (512) 18 19 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 20 21 #define CMD_INDEX_READ 0 22 #define CMD_INDEX_READSTATUS 1 23 #define CMD_INDEX_WRITEENABLE 2 24 #define CMD_INDEX_WRITE 4 25 26 #define CMD_LUT_SEQ_IDX_READ 0 27 #define CMD_LUT_SEQ_IDX_READSTATUS 1 28 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 29 #define CMD_LUT_SEQ_IDX_WRITE 9 30 31 #define CMD_SDR 0x01 32 #define CMD_DDR 0x21 33 #define RADDR_SDR 0x02 34 #define RADDR_DDR 0x22 35 #define CADDR_SDR 0x03 36 #define CADDR_DDR 0x23 37 #define MODE1_SDR 0x04 38 #define MODE1_DDR 0x24 39 #define MODE2_SDR 0x05 40 #define MODE2_DDR 0x25 41 #define MODE4_SDR 0x06 42 #define MODE4_DDR 0x26 43 #define MODE8_SDR 0x07 44 #define MODE8_DDR 0x27 45 #define WRITE_SDR 0x08 46 #define WRITE_DDR 0x28 47 #define READ_SDR 0x09 48 #define READ_DDR 0x29 49 #define LEARN_SDR 0x0A 50 #define LEARN_DDR 0x2A 51 #define DATSZ_SDR 0x0B 52 #define DATSZ_DDR 0x2B 53 #define DUMMY_SDR 0x0C 54 #define DUMMY_DDR 0x2C 55 #define DUMMY_RWDS_SDR 0x0D 56 #define DUMMY_RWDS_DDR 0x2D 57 #define JMP_ON_CS 0x1F 58 #define STOP 0 59 60 #define FLEXSPI_1PAD 0 61 #define FLEXSPI_2PAD 1 62 #define FLEXSPI_4PAD 2 63 #define FLEXSPI_8PAD 3 64 65 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 66 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 67 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 68 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 69 70 /* For flexspi_mem_config.serialClkFreq */ 71 #if defined(CONFIG_SOC_MIMXRT1011) 72 enum { 73 kFlexSpiSerialClk_30MHz = 1, 74 kFlexSpiSerialClk_50MHz = 2, 75 kFlexSpiSerialClk_60MHz = 3, 76 kFlexSpiSerialClk_75MHz = 4, 77 kFlexSpiSerialClk_80MHz = 5, 78 kFlexSpiSerialClk_100MHz = 6, 79 kFlexSpiSerialClk_120MHz = 7, 80 kFlexSpiSerialClk_133MHz = 8, 81 }; 82 #elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \ 83 defined(CONFIG_SOC_MIMXRT1024) 84 enum { 85 kFlexSpiSerialClk_30MHz = 1, 86 kFlexSpiSerialClk_50MHz = 2, 87 kFlexSpiSerialClk_60MHz = 3, 88 kFlexSpiSerialClk_75MHz = 4, 89 kFlexSpiSerialClk_80MHz = 5, 90 kFlexSpiSerialClk_100MHz = 6, 91 kFlexSpiSerialClk_133MHz = 7, 92 }; 93 #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \ 94 defined(CONFIG_SOC_SERIES_IMX_RT11XX) 95 enum { 96 kFlexSpiSerialClk_30MHz = 1, 97 kFlexSpiSerialClk_50MHz = 2, 98 kFlexSpiSerialClk_60MHz = 3, 99 kFlexSpiSerialClk_75MHz = 4, 100 kFlexSpiSerialClk_80MHz = 5, 101 kFlexSpiSerialClk_100MHz = 6, 102 kFlexSpiSerialClk_133MHz = 7, 103 kFlexSpiSerialClk_166MHz = 8, 104 kFlexSpiSerialClk_200MHz = 9, 105 }; 106 #elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \ 107 defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064) 108 enum { 109 kFlexSpiSerialClk_30MHz = 1, 110 kFlexSpiSerialClk_50MHz = 2, 111 kFlexSpiSerialClk_60MHz = 3, 112 kFlexSpiSerialClk_75MHz = 4, 113 kFlexSpiSerialClk_80MHz = 5, 114 kFlexSpiSerialClk_100MHz = 6, 115 kFlexSpiSerialClk_120MHz = 7, 116 kFlexSpiSerialClk_133MHz = 8, 117 kFlexSpiSerialClk_166MHz = 9, 118 }; 119 #else 120 #error "kFlexSpiSerialClk is not defined for this SoC" 121 #endif 122 123 /* For flexspi_mem_config.controllerMiscOption */ 124 enum { 125 kFlexSpiClk_SDR, 126 kFlexSpiClk_DDR, 127 }; 128 129 /* For flexspi_mem_config.readSampleClkSrc */ 130 enum { 131 kFlexSPIReadSampleClk_LoopbackInternally = 0, 132 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 133 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 134 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 135 }; 136 137 /* For flexspi_mem_config.controllerMiscOption */ 138 enum { 139 /* !< Bit for Differential clock enable */ 140 kFlexSpiMiscOffset_DiffClkEnable = 0, 141 /* !< Bit for CK2 enable */ 142 kFlexSpiMiscOffset_Ck2Enable = 1, 143 /* !< Bit for Parallel mode enable */ 144 kFlexSpiMiscOffset_ParallelEnable = 2, 145 /* !< Bit for Word Addressable enable */ 146 kFlexSpiMiscOffset_WordAddressableEnable = 3, 147 /* !< Bit for Safe Configuration Frequency enable */ 148 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, 149 /* !< Bit for Pad setting override enable */ 150 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, 151 /* !< Bit for DDR clock configuration indication. */ 152 kFlexSpiMiscOffset_DdrModeEnable = 6, 153 }; 154 155 /* For flexspi_mem_config.deviceType */ 156 enum { 157 /* !< Flash devices are Serial NOR */ 158 kFlexSpiDeviceType_SerialNOR = 1, 159 /* !< Flash devices are Serial NAND */ 160 kFlexSpiDeviceType_SerialNAND = 2, 161 /* !< Flash devices are Serial RAM/HyperFLASH */ 162 kFlexSpiDeviceType_SerialRAM = 3, 163 /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ 164 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, 165 /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ 166 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, 167 }; 168 169 /* For flexspi_mem_config.sflashPadType */ 170 enum { 171 kSerialFlash_1Pad = 1, 172 kSerialFlash_2Pads = 2, 173 kSerialFlash_4Pads = 4, 174 kSerialFlash_8Pads = 8, 175 }; 176 177 enum { 178 /* !< Generic command, for example: configure dummy cycles, drive strength, etc */ 179 kDeviceConfigCmdType_Generic, 180 /* !< Quad Enable command */ 181 kDeviceConfigCmdType_QuadEnable, 182 /* !< Switch from SPI to DPI/QPI/OPI mode */ 183 kDeviceConfigCmdType_Spi2Xpi, 184 /* !< Switch from DPI/QPI/OPI to SPI mode */ 185 kDeviceConfigCmdType_Xpi2Spi, 186 /* !< Switch to 0-4-4/0-8-8 mode */ 187 kDeviceConfigCmdType_Spi2NoCmd, 188 /* !< Reset device command */ 189 kDeviceConfigCmdType_Reset, 190 }; 191 192 struct flexspi_lut_seq_t { 193 uint8_t seqNum; 194 uint8_t seqId; 195 uint16_t reserved; 196 }; 197 198 struct flexspi_mem_config_t { 199 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ 200 uint32_t tag; 201 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ 202 uint32_t version; 203 /* !< [0x008-0x00b] Reserved for future use */ 204 uint32_t reserved0; 205 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 206 uint8_t readSampleClkSrc; 207 /* !< [0x00d-0x00d] CS hold time, default value: 3 */ 208 uint8_t csHoldTime; 209 /* !< [0x00e-0x00e] CS setup time, default value: 3 */ 210 uint8_t csSetupTime; 211 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */ 212 uint8_t columnAddressWidth; 213 /* ! Serial NAND, need to refer to datasheet */ 214 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ 215 uint8_t deviceModeCfgEnable; 216 /* !< [0x011-0x011] Specify the configuration command 217 * type:Quad Enable, DPI/QPI/OPI switch, 218 */ 219 uint8_t deviceModeType; 220 /* ! Generic configuration, etc. */ 221 /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for */ 222 uint16_t waitTimeCfgCommands; 223 /* ! DPI/QPI/OPI switch or reset command */ 224 /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt */ 225 struct flexspi_lut_seq_t deviceModeSeq; 226 /* ! sequence number, [31:16] Reserved */ 227 /* !< [0x018-0x01b] Argument/Parameter for device configuration */ 228 uint32_t deviceModeArg; 229 /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ 230 uint8_t configCmdEnable; 231 /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 232 uint8_t configModeType[3]; 233 /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar as 234 * deviceModeSeq 235 */ 236 struct flexspi_lut_seq_t configCmdSeqs[3]; 237 /* !< [0x02c-0x02f] Reserved for future use */ 238 uint32_t reserved1; 239 /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ 240 uint32_t configCmdArgs[3]; 241 /* !< [0x03c-0x03f] Reserved for future use */ 242 uint32_t reserved2; 243 /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more */ 244 uint32_t controllerMiscOption; 245 /* ! details */ 246 /* !< [0x044-0x044] Device Type: See Flash Type Definition for more details */ 247 uint8_t deviceType; 248 /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ 249 uint8_t sflashPadType; 250 /* !< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot */ 251 uint8_t serialClkFreq; 252 /* ! Chapter for more details */ 253 /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot */ 254 uint8_t lutCustomSeqEnable; 255 /* ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ 256 /* !< [0x048-0x04f] Reserved for future use */ 257 uint32_t reserved3[2]; 258 /* !< [0x050-0x053] Size of Flash connected to A1 */ 259 uint32_t sflashA1Size; 260 /* !< [0x054-0x057] Size of Flash connected to A2 */ 261 uint32_t sflashA2Size; 262 /* !< [0x058-0x05b] Size of Flash connected to B1 */ 263 uint32_t sflashB1Size; 264 /* !< [0x05c-0x05f] Size of Flash connected to B2 */ 265 uint32_t sflashB2Size; 266 /* !< [0x060-0x063] CS pad setting override value */ 267 uint32_t csPadSettingOverride; 268 /* !< [0x064-0x067] SCK pad setting override value */ 269 uint32_t sclkPadSettingOverride; 270 /* !< [0x068-0x06b] data pad setting override value */ 271 uint32_t dataPadSettingOverride; 272 /* !< [0x06c-0x06f] DQS pad setting override value */ 273 uint32_t dqsPadSettingOverride; 274 /* !< [0x070-0x073] Timeout threshold for read status command */ 275 uint32_t timeoutInMs; 276 /* !< [0x074-0x077] CS deselect interval between two commands */ 277 uint32_t commandInterval; 278 /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns */ 279 uint16_t dataValidTime[2]; 280 /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ 281 uint16_t busyOffset; 282 /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - */ 283 uint16_t busyBitPolarity; 284 /* ! busy flag is 0 when flash device is busy */ 285 /* !< [0x080-0x17f] Lookup table holds Flash command sequences */ 286 uint32_t lookupTable[64]; 287 /* !< [0x180-0x1af] Customizable LUT Sequences */ 288 struct flexspi_lut_seq_t lutCustomSeq[12]; 289 /* !< [0x1b0-0x1bf] Reserved for future use */ 290 uint32_t reserved4[4]; 291 }; 292 293 #define NOR_CMD_INDEX_READ CMD_INDEX_READ 294 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS 295 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE 296 #define NOR_CMD_INDEX_ERASESECTOR 3 297 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE 298 #define NOR_CMD_INDEX_CHIPERASE 5 299 #define NOR_CMD_INDEX_DUMMY 6 300 #define NOR_CMD_INDEX_ERASEBLOCK 7 301 302 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ 303 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS 304 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 305 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE 306 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 307 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 308 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 309 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE 310 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 311 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 312 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 313 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 314 315 struct flexspi_nor_config_t { 316 /* !< Common memory configuration info via FlexSPI */ 317 struct flexspi_mem_config_t memConfig; 318 /* !< Page size of Serial NOR */ 319 uint32_t pageSize; 320 /* !< Sector size of Serial NOR */ 321 uint32_t sectorSize; 322 /* !< Clock frequency for IP command */ 323 uint8_t ipcmdSerialClkFreq; 324 /* !< Sector/Block size is the same */ 325 uint8_t isUniformBlockSize; 326 /* !< Reserved for future use */ 327 uint8_t reserved0[2]; 328 /* !< Serial NOR Flash type: 0/1/2/3 */ 329 uint8_t serialNorType; 330 /* !< Need to exit NoCmd mode before other IP command */ 331 uint8_t needExitNoCmdMode; 332 /* !< Half the Serial Clock for non-read command: true/false */ 333 uint8_t halfClkForNonReadCmd; 334 /* !< Need to Restore NoCmd mode after IP command execution */ 335 uint8_t needRestoreNoCmdMode; 336 /* !< Block size */ 337 uint32_t blockSize; 338 /* !< Reserved for future use */ 339 uint32_t reserve2[11]; 340 }; 341 342 #ifdef __cplusplus 343 extern "C" { 344 #endif 345 346 #ifdef __cplusplus 347 } 348 #endif 349 #endif 350
