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Searched refs:gpio_irq_base (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_sifive.c51 uint32_t gpio_irq_base; member
108 (uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS)); in gpio_sifive_irq_handler()
247 irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
259 irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
273 irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
365 .gpio_irq_base = DT_INST_IRQN(0),
Dgpio_mchp_mss.c50 uint32_t gpio_irq_base; member
242 .gpio_irq_base = DT_INST_IRQN(n), \