Searched refs:gclk_core_id (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-Core-3.5.0/drivers/can/ |
| D | can_sam0.c | 28 uint16_t gclk_core_id; member
111 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK7 in can_sam0_clock_enable()
202 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch), \
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_sam0.c | 32 uint16_t gclk_core_id; member
649 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in spi_sam0_init()
722 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_sam0.c | 34 uint16_t gclk_core_id; member
705 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in i2c_sam0_initialize()
814 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_sam0.c | 41 uint16_t gclk_core_id; member
515 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in uart_sam0_init()
1282 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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