1 /*
2 * Copyright (c) 2022 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_enhance_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/pm/policy.h>
15 #include <errno.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/sys/util.h>
19
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(i2c_ite_enhance, CONFIG_I2C_LOG_LEVEL);
22
23 #include "i2c-priv.h"
24
25 /* Start smbus session from idle state */
26 #define I2C_MSG_START BIT(5)
27
28 #define I2C_LINE_SCL_HIGH BIT(0)
29 #define I2C_LINE_SDA_HIGH BIT(1)
30 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
31
32 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
33 /* Reserved 5 bytes for ID and CMD_x. */
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
35
36 /* Repeat Start. */
37 #define I2C_CQ_CMD_L_RS BIT(7)
38 /*
39 * R/W (Read/ Write) decides the I2C read or write direction.
40 * 1: read, 0: write
41 */
42 #define I2C_CQ_CMD_L_RW BIT(6)
43 /* P (STOP) is the I2C STOP condition. */
44 #define I2C_CQ_CMD_L_P BIT(5)
45 /* E (End) is this device end flag. */
46 #define I2C_CQ_CMD_L_E BIT(4)
47 /* LA (Last ACK) is Last ACK in master receiver. */
48 #define I2C_CQ_CMD_L_LA BIT(3)
49 /* bit[2:0] are number of transfer out or receive data which depends on R/W. */
50 #define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0)
51
52 struct i2c_cq_packet {
53 uint8_t id;
54 uint8_t cmd_l;
55 uint8_t cmd_h;
56 uint8_t wdata[0];
57 };
58 #endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
59
60 struct i2c_enhance_config {
61 void (*irq_config_func)(void);
62 uint32_t bitrate;
63 uint8_t *base;
64 uint8_t i2c_irq_base;
65 uint8_t port;
66 /* SCL GPIO cells */
67 struct gpio_dt_spec scl_gpios;
68 /* SDA GPIO cells */
69 struct gpio_dt_spec sda_gpios;
70 /* I2C alternate configuration */
71 const struct pinctrl_dev_config *pcfg;
72 uint8_t prescale_scl_low;
73 uint32_t clock_gate_offset;
74 bool target_enable;
75 bool target_pio_mode;
76 };
77
78 enum i2c_pin_fun {
79 SCL = 0,
80 SDA,
81 };
82
83 enum i2c_ch_status {
84 I2C_CH_NORMAL = 0,
85 I2C_CH_REPEAT_START,
86 I2C_CH_WAIT_READ,
87 I2C_CH_WAIT_NEXT_XFER,
88 };
89
90 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
91 struct i2c_host_cq_buffer {
92 /* Command queue tx payload. */
93 uint8_t i2c_cq_mode_tx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
94 /* Command queue rx payload. */
95 uint8_t i2c_cq_mode_rx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
96 };
97 #endif
98 #ifdef CONFIG_I2C_TARGET
99 /*
100 * When accessing data exceeds the maximum buffer, the actual reload address
101 * is one byte more than the maximum buffer size. Therefore, it is necessary to
102 * have a buffer in place to prevent overwriting other memory.
103 */
104 #define PROTECT_MEM_BUF 4
105 struct i2c_target_dma_buffer {
106 /* Target mode DMA output buffer. */
107 uint8_t __aligned(4)
108 out_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
109 /* Target mode DMA input buffer. */
110 uint8_t __aligned(4)
111 in_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
112 };
113 #endif
114
115 struct i2c_enhance_data {
116 enum i2c_ch_status i2ccs;
117 struct i2c_msg *active_msg;
118 struct k_mutex mutex;
119 struct k_sem device_sync_sem;
120 /* Index into output data */
121 size_t widx;
122 /* Index into input data */
123 size_t ridx;
124 /* operation freq of i2c */
125 uint32_t bus_freq;
126 /* Error code, if any */
127 uint32_t err;
128 /* address of device */
129 uint16_t addr_16bit;
130 /* wait for stop bit interrupt */
131 uint8_t stop;
132 /* Number of messages. */
133 uint8_t num_msgs;
134 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
135 /* Store command queue mode messages. */
136 struct i2c_msg *cq_msgs;
137 #endif
138 #ifdef CONFIG_I2C_TARGET
139 struct i2c_target_config *target_cfg;
140 uint32_t buffer_size;
141 int target_nack;
142 bool target_attached;
143 #endif
144 union {
145 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
146 struct i2c_host_cq_buffer host_buffer;
147 #endif
148 #ifdef CONFIG_I2C_TARGET
149 struct i2c_target_dma_buffer target_buffer;
150 #endif
151 };
152 };
153
154 enum enhanced_i2c_transfer_direct {
155 TX_DIRECT,
156 RX_DIRECT,
157 };
158
159 enum enhanced_i2c_ctl {
160 /* Hardware reset */
161 E_HW_RST = 0x01,
162 /* Stop */
163 E_STOP = 0x02,
164 /* Start & Repeat start */
165 E_START = 0x04,
166 /* Acknowledge */
167 E_ACK = 0x08,
168 /* State reset */
169 E_STS_RST = 0x10,
170 /* Mode select */
171 E_MODE_SEL = 0x20,
172 /* I2C interrupt enable */
173 E_INT_EN = 0x40,
174 /* 0 : Standard mode , 1 : Receive mode */
175 E_RX_MODE = 0x80,
176 /* State reset and hardware reset */
177 E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
178 /* Generate start condition and transmit slave address */
179 E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
180 /* Generate stop condition */
181 E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
182 /* Start with command queue mode */
183 E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START),
184 };
185
186 enum enhanced_i2c_host_status {
187 /* ACK receive */
188 E_HOSTA_ACK = 0x01,
189 /* Interrupt pending */
190 E_HOSTA_INTP = 0x02,
191 /* Read/Write */
192 E_HOSTA_RW = 0x04,
193 /* Time out error */
194 E_HOSTA_TMOE = 0x08,
195 /* Arbitration lost */
196 E_HOSTA_ARB = 0x10,
197 /* Bus busy */
198 E_HOSTA_BB = 0x20,
199 /* Address match */
200 E_HOSTA_AM = 0x40,
201 /* Byte done status */
202 E_HOSTA_BDS = 0x80,
203 /* time out or lost arbitration */
204 E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
205 /* Byte transfer done and ACK receive */
206 E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
207 };
208
209 enum i2c_reset_cause {
210 I2C_RC_NO_IDLE_FOR_START = 1,
211 I2C_RC_TIMEOUT,
212 };
213
214 #ifdef CONFIG_I2C_TARGET
215 enum enhanced_i2c_target_status {
216 /* Time out error */
217 E_TARGET_TMOE = 0x08,
218 /* Arbitration lost */
219 E_TARGET_ARB = 0x10,
220 /* Time out or lost arbitration */
221 E_TARGET_ANY_ERROR = (E_TARGET_TMOE | E_TARGET_ARB),
222 };
223 #endif
224
i2c_parsing_return_value(const struct device * dev)225 static int i2c_parsing_return_value(const struct device *dev)
226 {
227 struct i2c_enhance_data *data = dev->data;
228
229 if (!data->err) {
230 return 0;
231 }
232
233 /* Connection timed out */
234 if (data->err == ETIMEDOUT) {
235 return -ETIMEDOUT;
236 }
237
238 /* The device does not respond ACK */
239 if (data->err == E_HOSTA_ACK) {
240 return -ENXIO;
241 } else {
242 return -EIO;
243 }
244 }
245
i2c_get_line_levels(const struct device * dev)246 static int i2c_get_line_levels(const struct device *dev)
247 {
248 const struct i2c_enhance_config *config = dev->config;
249 uint8_t *base = config->base;
250 int pin_sts = 0;
251
252 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) {
253 pin_sts |= I2C_LINE_SCL_HIGH;
254 }
255
256 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) {
257 pin_sts |= I2C_LINE_SDA_HIGH;
258 }
259
260 return pin_sts;
261 }
262
i2c_is_busy(const struct device * dev)263 static int i2c_is_busy(const struct device *dev)
264 {
265 const struct i2c_enhance_config *config = dev->config;
266 uint8_t *base = config->base;
267
268 return (IT8XXX2_I2C_STR(base) & E_HOSTA_BB);
269 }
270
i2c_bus_not_available(const struct device * dev)271 static int i2c_bus_not_available(const struct device *dev)
272 {
273 if (i2c_is_busy(dev) ||
274 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
275 return -EIO;
276 }
277
278 return 0;
279 }
280
i2c_reset(const struct device * dev)281 static void i2c_reset(const struct device *dev)
282 {
283 const struct i2c_enhance_config *config = dev->config;
284 uint8_t *base = config->base;
285
286 /* State reset and hardware reset */
287 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
288 }
289
290 /* Set clock frequency for i2c port D, E , or F */
i2c_enhanced_port_set_frequency(const struct device * dev,int freq_hz)291 static void i2c_enhanced_port_set_frequency(const struct device *dev,
292 int freq_hz)
293 {
294 const struct i2c_enhance_config *config = dev->config;
295 uint32_t clk_div, psr, pll_clock;
296 uint8_t *base = config->base;
297
298 pll_clock = chip_get_pll_freq();
299 /*
300 * Let psr(Prescale) = IT8XXX2_I2C_PSR(p_ch)
301 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
302 * SMBus clock = pll_clock / clk_div
303 * SMBus clock cycle = 1 / SMBus clock
304 * 1 SCL cycle = 1 / freq
305 * 1 / freq = 2 x (psr + 2) x (1 / (pll_clock / clk_div))
306 * psr = ((pll_clock / clk_div) x (1 / freq) x (1 / 2)) - 2
307 */
308 if (freq_hz) {
309 /* Get SMBus clock divide value */
310 clk_div = (IT8XXX2_ECPM_SCDCR2 & 0x0F) + 1U;
311 /* Calculate PSR value */
312 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U;
313 /* Set psr value under 0xFD */
314 if (psr > 0xFD) {
315 psr = 0xFD;
316 }
317
318 /* Adjust SCL low period prescale */
319 psr += config->prescale_scl_low;
320
321 /* Set I2C Speed */
322 IT8XXX2_I2C_PSR(base) = psr & 0xFF;
323 IT8XXX2_I2C_HSPR(base) = psr & 0xFF;
324 }
325
326 }
327
i2c_enhance_configure(const struct device * dev,uint32_t dev_config_raw)328 static int i2c_enhance_configure(const struct device *dev,
329 uint32_t dev_config_raw)
330 {
331 const struct i2c_enhance_config *config = dev->config;
332 struct i2c_enhance_data *const data = dev->data;
333
334 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
335 return -EINVAL;
336 }
337
338 if (I2C_ADDR_10_BITS & dev_config_raw) {
339 return -EINVAL;
340 }
341
342 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
343
344 i2c_enhanced_port_set_frequency(dev, config->bitrate);
345
346 return 0;
347 }
348
i2c_enhance_get_config(const struct device * dev,uint32_t * dev_config)349 static int i2c_enhance_get_config(const struct device *dev, uint32_t *dev_config)
350 {
351 struct i2c_enhance_data *const data = dev->data;
352 uint32_t speed;
353
354 if (!data->bus_freq) {
355 LOG_ERR("The bus frequency is not initially configured.");
356 return -EIO;
357 }
358
359 switch (data->bus_freq) {
360 case I2C_SPEED_DT:
361 case I2C_SPEED_STANDARD:
362 case I2C_SPEED_FAST:
363 case I2C_SPEED_FAST_PLUS:
364 speed = I2C_SPEED_SET(data->bus_freq);
365 break;
366 default:
367 return -ERANGE;
368 }
369
370 *dev_config = (I2C_MODE_CONTROLLER | speed);
371
372 return 0;
373 }
374
enhanced_i2c_error(const struct device * dev)375 static int enhanced_i2c_error(const struct device *dev)
376 {
377 struct i2c_enhance_data *data = dev->data;
378 const struct i2c_enhance_config *config = dev->config;
379 uint8_t *base = config->base;
380 uint32_t i2c_str = IT8XXX2_I2C_STR(base);
381
382 if (i2c_str & E_HOSTA_ANY_ERROR) {
383 data->err = i2c_str & E_HOSTA_ANY_ERROR;
384 /* device does not respond ACK */
385 } else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
386 if (IT8XXX2_I2C_CTR(base) & E_ACK) {
387 data->err = E_HOSTA_ACK;
388 /* STOP */
389 IT8XXX2_I2C_CTR(base) = E_FINISH;
390 }
391 }
392
393 return data->err;
394 }
395
enhanced_i2c_start(const struct device * dev)396 static void enhanced_i2c_start(const struct device *dev)
397 {
398 const struct i2c_enhance_config *config = dev->config;
399 uint8_t *base = config->base;
400
401 /* reset i2c port */
402 i2c_reset(dev);
403 /* Set i2c frequency */
404 i2c_enhanced_port_set_frequency(dev, config->bitrate);
405 /*
406 * Set time out register.
407 * I2C D/E/F clock/data low timeout.
408 */
409 IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
410 /* bit1: Enable enhanced i2c module */
411 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
412 }
413
i2c_pio_trans_data(const struct device * dev,enum enhanced_i2c_transfer_direct direct,uint16_t trans_data,int first_byte)414 static void i2c_pio_trans_data(const struct device *dev,
415 enum enhanced_i2c_transfer_direct direct,
416 uint16_t trans_data, int first_byte)
417 {
418 struct i2c_enhance_data *data = dev->data;
419 const struct i2c_enhance_config *config = dev->config;
420 uint8_t *base = config->base;
421 uint32_t nack = 0;
422
423 if (first_byte) {
424 /* First byte must be slave address. */
425 IT8XXX2_I2C_DTR(base) = trans_data |
426 (direct == RX_DIRECT ? BIT(0) : 0);
427 /* start or repeat start signal. */
428 IT8XXX2_I2C_CTR(base) = E_START_ID;
429 } else {
430 if (direct == TX_DIRECT) {
431 /* Transmit data */
432 IT8XXX2_I2C_DTR(base) = (uint8_t)trans_data;
433 } else {
434 /*
435 * Receive data.
436 * Last byte should be NACK in the end of read cycle
437 */
438 if (((data->ridx + 1) == data->active_msg->len) &&
439 (data->active_msg->flags & I2C_MSG_STOP)) {
440 nack = 1;
441 }
442 }
443 /* Set hardware reset to start next transmission */
444 IT8XXX2_I2C_CTR(base) = E_INT_EN | E_MODE_SEL |
445 E_HW_RST | (nack ? 0 : E_ACK);
446 }
447 }
448
enhanced_i2c_tran_read(const struct device * dev)449 static int enhanced_i2c_tran_read(const struct device *dev)
450 {
451 struct i2c_enhance_data *data = dev->data;
452 const struct i2c_enhance_config *config = dev->config;
453 uint8_t *base = config->base;
454 uint8_t in_data = 0;
455
456 if (data->active_msg->flags & I2C_MSG_START) {
457 /* clear start flag */
458 data->active_msg->flags &= ~I2C_MSG_START;
459 enhanced_i2c_start(dev);
460 /* Direct read */
461 data->i2ccs = I2C_CH_WAIT_READ;
462 /* Send ID */
463 i2c_pio_trans_data(dev, RX_DIRECT, data->addr_16bit << 1, 1);
464 } else {
465 if (data->i2ccs) {
466 if (data->i2ccs == I2C_CH_WAIT_READ) {
467 data->i2ccs = I2C_CH_NORMAL;
468 /* Receive data */
469 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
470
471 /* data->active_msg->flags == I2C_MSG_RESTART */
472 } else {
473 /* Write to read */
474 data->i2ccs = I2C_CH_WAIT_READ;
475 /* Send ID */
476 i2c_pio_trans_data(dev, RX_DIRECT,
477 data->addr_16bit << 1, 1);
478 }
479 } else {
480 if (data->ridx < data->active_msg->len) {
481 /* read data */
482 *(data->active_msg->buf++) = IT8XXX2_I2C_DRR(base);
483 data->ridx++;
484 /* done */
485 if (data->ridx == data->active_msg->len) {
486 data->active_msg->len = 0;
487 if (data->active_msg->flags & I2C_MSG_STOP) {
488 data->i2ccs = I2C_CH_NORMAL;
489 IT8XXX2_I2C_CTR(base) = E_FINISH;
490 /* wait for stop bit interrupt */
491 data->stop = 1;
492 return 1;
493 }
494 /* End the transaction */
495 data->i2ccs = I2C_CH_WAIT_READ;
496 return 0;
497 }
498 /* read next byte */
499 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
500 }
501 }
502 }
503 return 1;
504 }
505
enhanced_i2c_tran_write(const struct device * dev)506 static int enhanced_i2c_tran_write(const struct device *dev)
507 {
508 struct i2c_enhance_data *data = dev->data;
509 const struct i2c_enhance_config *config = dev->config;
510 uint8_t *base = config->base;
511 uint8_t out_data;
512
513 if (data->active_msg->flags & I2C_MSG_START) {
514 /* Clear start bit */
515 data->active_msg->flags &= ~I2C_MSG_START;
516 enhanced_i2c_start(dev);
517 /* Send ID */
518 i2c_pio_trans_data(dev, TX_DIRECT, data->addr_16bit << 1, 1);
519 } else {
520 /* Host has completed the transmission of a byte */
521 if (data->widx < data->active_msg->len) {
522 out_data = *(data->active_msg->buf++);
523 data->widx++;
524
525 /* Send Byte */
526 i2c_pio_trans_data(dev, TX_DIRECT, out_data, 0);
527 if (data->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
528 data->i2ccs = I2C_CH_NORMAL;
529 }
530 } else {
531 /* done */
532 data->active_msg->len = 0;
533 if (data->active_msg->flags & I2C_MSG_STOP) {
534 IT8XXX2_I2C_CTR(base) = E_FINISH;
535 /* wait for stop bit interrupt */
536 data->stop = 1;
537 } else {
538 /* Direct write with direct read */
539 data->i2ccs = I2C_CH_WAIT_NEXT_XFER;
540 return 0;
541 }
542 }
543 }
544 return 1;
545 }
546
i2c_transaction(const struct device * dev)547 static int i2c_transaction(const struct device *dev)
548 {
549 struct i2c_enhance_data *data = dev->data;
550 const struct i2c_enhance_config *config = dev->config;
551 uint8_t *base = config->base;
552
553 /* no error */
554 if (!(enhanced_i2c_error(dev))) {
555 if (!data->stop) {
556 /*
557 * The return value indicates if there is more data
558 * to be read or written. If the return value = 1,
559 * it means that the interrupt cannot be disable and
560 * continue to transmit data.
561 */
562 if (data->active_msg->flags & I2C_MSG_READ) {
563 return enhanced_i2c_tran_read(dev);
564 } else {
565 return enhanced_i2c_tran_write(dev);
566 }
567 }
568 }
569 /* reset i2c port */
570 i2c_reset(dev);
571 IT8XXX2_I2C_CTR1(base) = 0;
572
573 data->stop = 0;
574 /* done doing work */
575 return 0;
576 }
577
i2c_enhance_pio_transfer(const struct device * dev,struct i2c_msg * msgs)578 static int i2c_enhance_pio_transfer(const struct device *dev,
579 struct i2c_msg *msgs)
580 {
581 struct i2c_enhance_data *data = dev->data;
582 const struct i2c_enhance_config *config = dev->config;
583 int res;
584
585 if (data->i2ccs == I2C_CH_NORMAL) {
586 struct i2c_msg *start_msg = &msgs[0];
587
588 start_msg->flags |= I2C_MSG_START;
589 }
590
591 for (int i = 0; i < data->num_msgs; i++) {
592
593 data->widx = 0;
594 data->ridx = 0;
595 data->err = 0;
596 data->active_msg = &msgs[i];
597
598 /*
599 * Start transaction.
600 * The return value indicates if the initial configuration
601 * of I2C transaction for read or write has been completed.
602 */
603 if (i2c_transaction(dev)) {
604 /* Enable I2C interrupt. */
605 irq_enable(config->i2c_irq_base);
606 }
607 /* Wait for the transfer to complete */
608 /* TODO: the timeout should be adjustable */
609 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
610 /*
611 * The irq will be enabled at the condition of start or
612 * repeat start of I2C. If timeout occurs without being
613 * wake up during suspend(ex: interrupt is not fired),
614 * the irq should be disabled immediately.
615 */
616 irq_disable(config->i2c_irq_base);
617 /*
618 * The transaction is dropped on any error(timeout, NACK, fail,
619 * bus error, device error).
620 */
621 if (data->err) {
622 break;
623 }
624
625 if (res != 0) {
626 data->err = ETIMEDOUT;
627 /* reset i2c port */
628 i2c_reset(dev);
629 LOG_ERR("I2C ch%d:0x%X reset cause %d",
630 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
631 /* If this message is sent fail, drop the transaction. */
632 break;
633 }
634 }
635
636 /* reset i2c channel status */
637 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
638 data->i2ccs = I2C_CH_NORMAL;
639 }
640
641 return data->err;
642 }
643
644 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
enhanced_i2c_set_cmd_addr_regs(const struct device * dev)645 static void enhanced_i2c_set_cmd_addr_regs(const struct device *dev)
646 {
647 const struct i2c_enhance_config *config = dev->config;
648 struct i2c_enhance_data *data = dev->data;
649 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
650 uint32_t dlm_base;
651 uint8_t *base = config->base;
652
653 /* Set "Address Register" to store the I2C data. */
654 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_rx_dlm & 0xffffff;
655 IT8XXX2_I2C_RAMH2A(base) = (dlm_base >> 16) & 0xff;
656 IT8XXX2_I2C_RAMHA(base) = (dlm_base >> 8) & 0xff;
657 IT8XXX2_I2C_RAMLA(base) = dlm_base & 0xff;
658
659 /* Set "Command Address Register" to get commands. */
660 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_tx_dlm & 0xffffff;
661 IT8XXX2_I2C_CMD_ADDH2(base) = (dlm_base >> 16) & 0xff;
662 IT8XXX2_I2C_CMD_ADDH(base) = (dlm_base >> 8) & 0xff;
663 IT8XXX2_I2C_CMD_ADDL(base) = dlm_base & 0xff;
664 }
665
enhanced_i2c_cq_write(const struct device * dev)666 static void enhanced_i2c_cq_write(const struct device *dev)
667 {
668 struct i2c_enhance_data *data = dev->data;
669 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
670 struct i2c_cq_packet *i2c_cq_pckt;
671 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
672 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
673
674 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
675 /* Set commands in RAM. */
676 i2c_cq_pckt->id = data->addr_16bit << 1;
677 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
678 i2c_cq_pckt->cmd_h = num_bit_10_3;
679 for (int i = 0; i < data->cq_msgs[0].len; i++) {
680 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
681 }
682 }
683
enhanced_i2c_cq_read(const struct device * dev)684 static void enhanced_i2c_cq_read(const struct device *dev)
685 {
686 struct i2c_enhance_data *data = dev->data;
687 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
688 struct i2c_cq_packet *i2c_cq_pckt;
689 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
690 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
691
692 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
693 /* Set commands in RAM. */
694 i2c_cq_pckt->id = data->addr_16bit << 1;
695 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P |
696 I2C_CQ_CMD_L_E | num_bit_2_0;
697 i2c_cq_pckt->cmd_h = num_bit_10_3;
698 }
699
enhanced_i2c_cq_write_to_read(const struct device * dev)700 static void enhanced_i2c_cq_write_to_read(const struct device *dev)
701 {
702 struct i2c_enhance_data *data = dev->data;
703 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
704 struct i2c_cq_packet *i2c_cq_pckt;
705 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
706 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
707 int i;
708
709 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
710 /* Set commands in RAM. (command byte for write) */
711 i2c_cq_pckt->id = data->addr_16bit << 1;
712 i2c_cq_pckt->cmd_l = num_bit_2_0;
713 i2c_cq_pckt->cmd_h = num_bit_10_3;
714 for (i = 0; i < data->cq_msgs[0].len; i++) {
715 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
716 }
717
718 /* Set commands in RAM. (command byte for read) */
719 num_bit_2_0 = (data->cq_msgs[1].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
720 num_bit_10_3 = ((data->cq_msgs[1].len - 1) >> 3) & 0xff;
721 i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
722 I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
723 i2c_cq_pckt->wdata[i] = num_bit_10_3;
724 }
725
enhanced_i2c_cq_isr(const struct device * dev)726 static int enhanced_i2c_cq_isr(const struct device *dev)
727 {
728 struct i2c_enhance_data *data = dev->data;
729 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
730 const struct i2c_enhance_config *config = dev->config;
731 uint8_t *base = config->base;
732
733 /* Device 1 finish IRQ. */
734 if (IT8XXX2_I2C_FST(base) & IT8XXX2_I2C_FST_DEV1_IRQ) {
735 uint8_t msgs_idx = data->num_msgs - 1;
736
737 /* Get data if this is a read transaction. */
738 for (int i = 0; i < data->cq_msgs[msgs_idx].len; i++) {
739 data->cq_msgs[msgs_idx].buf[i] =
740 host_buffer->i2c_cq_mode_rx_dlm[i];
741 }
742 } else {
743 /* Device 1 error have occurred. eg. nack, timeout... */
744 if (IT8XXX2_I2C_NST(base) & IT8XXX2_I2C_NST_ID_NACK) {
745 data->err = E_HOSTA_ACK;
746 } else {
747 data->err = IT8XXX2_I2C_STR(base) &
748 E_HOSTA_ANY_ERROR;
749 }
750 }
751 /* Reset bus. */
752 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
753 IT8XXX2_I2C_CTR1(base) = 0;
754
755 return 0;
756 }
757
enhanced_i2c_cmd_queue_trans(const struct device * dev)758 static int enhanced_i2c_cmd_queue_trans(const struct device *dev)
759 {
760 struct i2c_enhance_data *data = dev->data;
761 const struct i2c_enhance_config *config = dev->config;
762 uint8_t *base = config->base;
763
764 /* State reset and hardware reset. */
765 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
766 /* Set "PSR" registers to decide the i2c speed. */
767 i2c_enhanced_port_set_frequency(dev, config->bitrate);
768 /* Set time out register. port D, E, or F clock/data low timeout. */
769 IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
770
771 if (data->num_msgs == 2) {
772 /* I2C write to read of command queue mode. */
773 enhanced_i2c_cq_write_to_read(dev);
774 } else {
775 /* I2C read of command queue mode. */
776 if (data->cq_msgs[0].flags & I2C_MSG_READ) {
777 enhanced_i2c_cq_read(dev);
778 /* I2C write of command queue mode. */
779 } else {
780 enhanced_i2c_cq_write(dev);
781 }
782 }
783
784 /* Enable i2c module with command queue mode. */
785 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN | IT8XXX2_I2C_COMQ_EN;
786 /* One shot on device 1. */
787 IT8XXX2_I2C_MODE_SEL(base) = 0;
788 IT8XXX2_I2C_CTR2(base) = 1;
789 /*
790 * The EC processor(CPU) cannot be in the k_cpu_idle() and power
791 * policy during the transactions with the CQ mode(DMA mode).
792 * Otherwise, the EC processor would be clock gated.
793 */
794 chip_block_idle();
795 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
796 /* Start */
797 IT8XXX2_I2C_CTR(base) = E_START_CQ;
798
799 return 1;
800 }
801
i2c_enhance_cq_transfer(const struct device * dev,struct i2c_msg * msgs)802 static int i2c_enhance_cq_transfer(const struct device *dev,
803 struct i2c_msg *msgs)
804 {
805 struct i2c_enhance_data *data = dev->data;
806 const struct i2c_enhance_config *config = dev->config;
807 int res = 0;
808
809 data->err = 0;
810 data->cq_msgs = msgs;
811
812 /* Start transaction */
813 if (enhanced_i2c_cmd_queue_trans(dev)) {
814 /* Enable i2c interrupt */
815 irq_enable(config->i2c_irq_base);
816 }
817 /* Wait for the transfer to complete */
818 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
819
820 irq_disable(config->i2c_irq_base);
821
822 if (res != 0) {
823 data->err = ETIMEDOUT;
824 /* Reset i2c port. */
825 i2c_reset(dev);
826 LOG_ERR("I2C ch%d:0x%X reset cause %d",
827 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
828 }
829
830 /* Permit to enter power policy and idle mode. */
831 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
832 chip_permit_idle();
833
834 return data->err;
835 }
836
cq_mode_allowed(const struct device * dev,struct i2c_msg * msgs)837 static bool cq_mode_allowed(const struct device *dev, struct i2c_msg *msgs)
838 {
839 struct i2c_enhance_data *data = dev->data;
840
841 /*
842 * If the transaction of write or read is divided into two
843 * transfers(not two messages), the command queue mode does
844 * not support.
845 */
846 if (data->i2ccs != I2C_CH_NORMAL) {
847 return false;
848 }
849 /*
850 * When there is only one message, use the command queue transfer
851 * directly.
852 */
853 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP)) {
854 /* Read transfer payload too long, use PIO mode */
855 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
856 (msgs[0].len > CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
857 return false;
858 }
859 /* Write transfer payload too long, use PIO mode */
860 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
861 (msgs[0].len > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
862 return false;
863 }
864 /*
865 * Write of I2C target address without writing data, used by
866 * cmd_i2c_scan. Use PIO mode.
867 */
868 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
869 (msgs[0].len == 0)) {
870 return false;
871 }
872 return true;
873 }
874 /*
875 * When there are two messages, we need to judge whether or not there
876 * is I2C_MSG_RESTART flag from the second message, and then decide to
877 * do the command queue or PIO mode transfer.
878 */
879 if (data->num_msgs == 2) {
880 /*
881 * The first of two messages must be write.
882 * If the length of write to read transfer is greater than
883 * command queue payload size, there will execute PIO mode.
884 */
885 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
886 (msgs[0].len <= I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
887 /*
888 * The transfer is i2c_burst_read().
889 *
890 * e.g. msg[0].flags = I2C_MSG_WRITE;
891 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
892 * I2C_MSG_STOP;
893 */
894 if ((msgs[1].flags & I2C_MSG_RESTART) &&
895 ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
896 (msgs[1].flags & I2C_MSG_STOP) &&
897 (msgs[1].len <= CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
898 return true;
899 }
900 }
901 }
902
903 return false;
904 }
905 #endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
906
i2c_enhance_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)907 static int i2c_enhance_transfer(const struct device *dev,
908 struct i2c_msg *msgs,
909 uint8_t num_msgs, uint16_t addr)
910 {
911 struct i2c_enhance_data *data = dev->data;
912 int ret;
913
914 #ifdef CONFIG_I2C_TARGET
915 if (data->target_attached) {
916 LOG_ERR("Device is registered as target");
917 return -EBUSY;
918 }
919 #endif
920 /* Lock mutex of i2c controller */
921 k_mutex_lock(&data->mutex, K_FOREVER);
922
923 data->num_msgs = num_msgs;
924 data->addr_16bit = addr;
925 /*
926 * If the transaction of write to read is divided into two
927 * transfers, the repeat start transfer uses this flag to
928 * exclude checking bus busy.
929 */
930 if (data->i2ccs == I2C_CH_NORMAL) {
931 /* Make sure we're in a good state to start */
932 if (i2c_bus_not_available(dev)) {
933 /* Recovery I2C bus */
934 i2c_recover_bus(dev);
935 /*
936 * After resetting I2C bus, if I2C bus is not available
937 * (No external pull-up), drop the transaction.
938 */
939 if (i2c_bus_not_available(dev)) {
940 /* Unlock mutex of i2c controller */
941 k_mutex_unlock(&data->mutex);
942 return -EIO;
943 }
944 }
945 }
946
947 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
948 if (cq_mode_allowed(dev, msgs)) {
949 data->err = i2c_enhance_cq_transfer(dev, msgs);
950 } else
951 #endif
952 {
953 data->err = i2c_enhance_pio_transfer(dev, msgs);
954 }
955 /* Save return value. */
956 ret = i2c_parsing_return_value(dev);
957 /* Unlock mutex of i2c controller */
958 k_mutex_unlock(&data->mutex);
959
960 return ret;
961 }
962
963 #ifdef CONFIG_I2C_TARGET
target_i2c_isr_dma(const struct device * dev,uint8_t interrupt_status)964 static void target_i2c_isr_dma(const struct device *dev,
965 uint8_t interrupt_status)
966 {
967 struct i2c_enhance_data *data = dev->data;
968 const struct i2c_enhance_config *config = dev->config;
969 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
970 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
971 uint8_t *base = config->base;
972
973 /* Byte counter enable */
974 if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
975 IT8XXX2_I2C_BYTE_CNT_L(base) |=
976 (IT8XXX2_I2C_DMA_ADDR_RELOAD |
977 IT8XXX2_I2C_BYTE_CNT_ENABLE);
978 }
979 /* The number of received data exceeds the byte counter setting */
980 if (interrupt_status & IT8XXX2_I2C_CNT_HOLD) {
981 LOG_ERR("The excess data written starts "
982 "from the memory address:%p",
983 target_buffer->in_buffer +
984 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE);
985 }
986 /* Controller to write data */
987 if (interrupt_status & IT8XXX2_I2C_SLVDATAFLG) {
988 /* Number of receive data in target mode */
989 data->buffer_size =
990 ((IT8XXX2_I2C_SLV_NUM_H(base) << 8) |
991 IT8XXX2_I2C_SLV_NUM_L(base)) + 1;
992
993 /* Write data done callback function */
994 target_cb->buf_write_received(data->target_cfg,
995 target_buffer->in_buffer, data->buffer_size);
996 }
997 /* Controller to read data */
998 if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
999 uint32_t len;
1000 uint8_t *rdata = NULL;
1001
1002 /* Clear byte counter setting */
1003 IT8XXX2_I2C_BYTE_CNT_L(base) &=
1004 ~(IT8XXX2_I2C_DMA_ADDR_RELOAD |
1005 IT8XXX2_I2C_BYTE_CNT_ENABLE);
1006 /* Read data callback function */
1007 target_cb->buf_read_requested(data->target_cfg,
1008 &rdata, &len);
1009
1010 if (len > CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE) {
1011 LOG_ERR("The bufffer size exceeds "
1012 "I2C_TARGET_IT8XXX2_MAX_BUF_SIZE: len=%d",
1013 len);
1014 } else {
1015 memcpy(target_buffer->out_buffer, rdata, len);
1016 }
1017 }
1018 }
1019
target_i2c_isr_pio(const struct device * dev,uint8_t interrupt_status,uint8_t target_status)1020 static int target_i2c_isr_pio(const struct device *dev,
1021 uint8_t interrupt_status,
1022 uint8_t target_status)
1023 {
1024 struct i2c_enhance_data *data = dev->data;
1025 const struct i2c_enhance_config *config = dev->config;
1026 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
1027 int ret = 0;
1028 uint8_t *base = config->base;
1029 uint8_t val;
1030
1031 /* Target ID write flag */
1032 if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
1033 ret = target_cb->write_requested(data->target_cfg);
1034 }
1035 /* Target ID read flag */
1036 else if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
1037 if (!target_cb->read_requested(data->target_cfg, &val)) {
1038 IT8XXX2_I2C_DTR(base) = val;
1039 }
1040 }
1041 /* Byte transfer done */
1042 else if (target_status & IT8XXX2_I2C_BYTE_DONE) {
1043 /* Read of write */
1044 if (target_status & IT8XXX2_I2C_RW) {
1045 /* Host receiving, target transmitting */
1046 if (!target_cb->read_processed(data->target_cfg, &val)) {
1047 IT8XXX2_I2C_DTR(base) = val;
1048 }
1049 } else {
1050 /* Host transmitting, target receiving */
1051 val = IT8XXX2_I2C_DRR(base);
1052 ret = target_cb->write_received(data->target_cfg, val);
1053 }
1054 }
1055
1056 return ret;
1057 }
1058
target_i2c_isr(const struct device * dev)1059 static void target_i2c_isr(const struct device *dev)
1060 {
1061 struct i2c_enhance_data *data = dev->data;
1062 const struct i2c_enhance_config *config = dev->config;
1063 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
1064 uint8_t *base = config->base;
1065 uint8_t target_status = IT8XXX2_I2C_STR(base);
1066
1067 /* Any error */
1068 if (target_status & E_TARGET_ANY_ERROR) {
1069 goto end;
1070 }
1071
1072 /* Interrupt pending */
1073 if (target_status & IT8XXX2_I2C_INT_PEND) {
1074 uint8_t interrupt_status = IT8XXX2_I2C_IRQ_ST(base);
1075
1076 /* Determine whether the transaction uses PIO or DMA mode */
1077 if (config->target_pio_mode) {
1078 if (target_i2c_isr_pio(dev, interrupt_status, target_status) < 0) {
1079 /* NACK */
1080 IT8XXX2_I2C_CTR(base) &= ~IT8XXX2_I2C_ACK;
1081 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
1082 data->target_nack = 1;
1083 }
1084 } else {
1085 target_i2c_isr_dma(dev, interrupt_status);
1086 }
1087 /* Peripheral finish */
1088 if (interrupt_status & IT8XXX2_I2C_P_CLR) {
1089 /* Transfer done callback function */
1090 target_cb->stop(data->target_cfg);
1091
1092 if (data->target_nack) {
1093 /* Set acknowledge */
1094 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_ACK;
1095 data->target_nack = 0;
1096 }
1097 }
1098 /* Write clear the peripheral status */
1099 IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
1100 }
1101 end:
1102 /* Hardware reset */
1103 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
1104 }
1105 #endif
1106
i2c_enhance_isr(void * arg)1107 static void i2c_enhance_isr(void *arg)
1108 {
1109 struct device *dev = (struct device *)arg;
1110 struct i2c_enhance_data *data = dev->data;
1111 const struct i2c_enhance_config *config = dev->config;
1112
1113 #ifdef CONFIG_I2C_TARGET
1114 if (data->target_attached) {
1115 target_i2c_isr(dev);
1116 } else {
1117 #endif
1118 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
1119 uint8_t *base = config->base;
1120
1121 /* If done doing work, wake up the task waiting for the transfer */
1122 if (IT8XXX2_I2C_CTR1(base) & IT8XXX2_I2C_COMQ_EN) {
1123 if (enhanced_i2c_cq_isr(dev)) {
1124 return;
1125 }
1126 } else
1127 #endif
1128 {
1129 if (i2c_transaction(dev)) {
1130 return;
1131 }
1132 }
1133 irq_disable(config->i2c_irq_base);
1134 k_sem_give(&data->device_sync_sem);
1135 #ifdef CONFIG_I2C_TARGET
1136 }
1137 #endif
1138 }
1139
i2c_enhance_init(const struct device * dev)1140 static int i2c_enhance_init(const struct device *dev)
1141 {
1142 struct i2c_enhance_data *data = dev->data;
1143 const struct i2c_enhance_config *config = dev->config;
1144 uint8_t *base = config->base;
1145 uint32_t bitrate_cfg;
1146 int error, status;
1147
1148 #ifdef CONFIG_I2C_TARGET
1149 if (!config->target_enable) {
1150 #endif
1151 /* Initialize mutex and semaphore */
1152 k_mutex_init(&data->mutex);
1153 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1154
1155 /* Enable clock to specified peripheral */
1156 volatile uint8_t *reg = (volatile uint8_t *)
1157 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1158 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1159 *reg &= ~reg_mask;
1160
1161 /* Enable I2C function */
1162 /* Software reset */
1163 IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
1164 IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
1165 /* reset i2c port */
1166 i2c_reset(dev);
1167 /* bit1, Module enable */
1168 IT8XXX2_I2C_CTR1(base) = 0;
1169
1170 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
1171 /* Set command address registers. */
1172 enhanced_i2c_set_cmd_addr_regs(dev);
1173 #endif
1174
1175 /* Set clock frequency for I2C ports */
1176 if (config->bitrate == I2C_BITRATE_STANDARD ||
1177 config->bitrate == I2C_BITRATE_FAST ||
1178 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1179 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1180 } else {
1181 /* Device tree specified speed */
1182 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1183 }
1184
1185 error = i2c_enhance_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1186 data->i2ccs = I2C_CH_NORMAL;
1187
1188 if (error) {
1189 LOG_ERR("i2c: failure initializing");
1190 return error;
1191 }
1192 #ifdef CONFIG_I2C_TARGET
1193 }
1194 #endif
1195
1196 /* Set the pin to I2C alternate function. */
1197 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1198 if (status < 0) {
1199 LOG_ERR("Failed to configure I2C pins");
1200 return status;
1201 }
1202
1203
1204 return 0;
1205 }
1206
i2c_enhance_recover_bus(const struct device * dev)1207 static int i2c_enhance_recover_bus(const struct device *dev)
1208 {
1209 const struct i2c_enhance_config *config = dev->config;
1210 int i, status;
1211
1212 /* Set SCL of I2C as GPIO pin */
1213 gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT);
1214 /* Set SDA of I2C as GPIO pin */
1215 gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT);
1216
1217 /*
1218 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1219 * is mainly to ensure that gpio has enough time to go from
1220 * low to high or high to low.
1221 */
1222 /* Pull SCL and SDA pin to high */
1223 gpio_pin_set_dt(&config->scl_gpios, 1);
1224 gpio_pin_set_dt(&config->sda_gpios, 1);
1225 k_msleep(1);
1226
1227 /* Start condition */
1228 gpio_pin_set_dt(&config->sda_gpios, 0);
1229 k_msleep(1);
1230 gpio_pin_set_dt(&config->scl_gpios, 0);
1231 k_msleep(1);
1232
1233 /* 9 cycles of SCL with SDA held high */
1234 for (i = 0; i < 9; i++) {
1235 /* SDA */
1236 gpio_pin_set_dt(&config->sda_gpios, 1);
1237 /* SCL */
1238 gpio_pin_set_dt(&config->scl_gpios, 1);
1239 k_msleep(1);
1240 /* SCL */
1241 gpio_pin_set_dt(&config->scl_gpios, 0);
1242 k_msleep(1);
1243 }
1244 /* SDA */
1245 gpio_pin_set_dt(&config->sda_gpios, 0);
1246 k_msleep(1);
1247
1248 /* Stop condition */
1249 gpio_pin_set_dt(&config->scl_gpios, 1);
1250 k_msleep(1);
1251 gpio_pin_set_dt(&config->sda_gpios, 1);
1252 k_msleep(1);
1253
1254 /* Set GPIO back to I2C alternate function */
1255 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1256 if (status < 0) {
1257 LOG_ERR("Failed to configure I2C pins");
1258 return status;
1259 }
1260
1261 /* reset i2c port */
1262 i2c_reset(dev);
1263 LOG_ERR("I2C ch%d reset cause %d", config->port,
1264 I2C_RC_NO_IDLE_FOR_START);
1265
1266 return 0;
1267 }
1268
1269 #ifdef CONFIG_I2C_TARGET
i2c_enhance_target_register(const struct device * dev,struct i2c_target_config * target_cfg)1270 static int i2c_enhance_target_register(const struct device *dev,
1271 struct i2c_target_config *target_cfg)
1272 {
1273 const struct i2c_enhance_config *config = dev->config;
1274 struct i2c_enhance_data *data = dev->data;
1275 uint8_t *base = config->base;
1276
1277 if (!target_cfg) {
1278 return -EINVAL;
1279 }
1280
1281 if (target_cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
1282 return -ENOTSUP;
1283 }
1284
1285 if (data->target_attached) {
1286 return -EBUSY;
1287 }
1288
1289 data->target_cfg = target_cfg;
1290 data->target_attached = true;
1291
1292 /* Software reset */
1293 IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
1294 IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
1295 /* Disable the timeout setting when clock/data are in a low state */
1296 IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |
1297 IT8XXX2_I2C_SDA_TIMEOUT_EN);
1298 /* Bit stretching */
1299 IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;
1300 /* Peripheral address(8-bit) */
1301 IT8XXX2_I2C_IDR(base) = target_cfg->address << 1;
1302 /* I2C interrupt enable and set acknowledge */
1303 IT8XXX2_I2C_CTR(base) = IT8XXX2_I2C_INT_EN | IT8XXX2_I2C_HALT |
1304 IT8XXX2_I2C_ACK;
1305 /* Interrupt status write clear */
1306 IT8XXX2_I2C_IRQ_ST(base) = 0xff;
1307
1308 /* I2C target initial configuration of PIO mode */
1309 if (config->target_pio_mode) {
1310 /* Block to enter power policy. */
1311 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1312
1313 /* I2C module enable */
1314 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
1315 /* I2C target initial configuration of DMA mode */
1316 } else {
1317 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
1318 uint32_t in_data_addr, out_data_addr;
1319 int buf_size = CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE;
1320
1321 /* Clear read and write data buffer of DMA */
1322 memset(target_buffer->in_buffer, 0, buf_size);
1323 memset(target_buffer->out_buffer, 0, buf_size);
1324
1325 in_data_addr = (uint32_t)target_buffer->in_buffer & 0xffffff;
1326 out_data_addr = (uint32_t)target_buffer->out_buffer & 0xffffff;
1327 /*
1328 * DMA write target address register
1329 * for high order byte
1330 */
1331 IT8XXX2_I2C_RAMH2A(base) = in_data_addr >> 16;
1332 IT8XXX2_I2C_RAMHA(base) = in_data_addr >> 8;
1333 IT8XXX2_I2C_RAMLA(base) = in_data_addr;
1334 /*
1335 * DMA read target address register
1336 * for high order byte
1337 */
1338 IT8XXX2_I2C_CMD_ADDH2(base) = out_data_addr >> 16;
1339 IT8XXX2_I2C_RAMHA2(base) = out_data_addr >> 8;
1340 IT8XXX2_I2C_RAMLA2(base) = out_data_addr;
1341
1342 /* Byte counter setting */
1343 /* This register indicates byte count[10:3]. */
1344 IT8XXX2_I2C_BYTE_CNT_H(base) =
1345 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE >> 3;
1346 /* This register indicates byte count[2:0]. */
1347 IT8XXX2_I2C_BYTE_CNT_L(base) =
1348 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE & GENMASK(2, 0);
1349
1350 /*
1351 * The EC processor(CPU) cannot be in the k_cpu_idle() and power
1352 * policy during the transactions with the CQ mode(DMA mode).
1353 * Otherwise, the EC processor would be clock gated.
1354 */
1355 chip_block_idle();
1356 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1357
1358 /* I2C module enable and command queue mode */
1359 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_COMQ_EN | IT8XXX2_I2C_MDL_EN;
1360 }
1361
1362 ite_intc_isr_clear(config->i2c_irq_base);
1363 irq_enable(config->i2c_irq_base);
1364
1365 return 0;
1366 }
1367
i2c_enhance_target_unregister(const struct device * dev,struct i2c_target_config * cfg)1368 static int i2c_enhance_target_unregister(const struct device *dev,
1369 struct i2c_target_config *cfg)
1370 {
1371 const struct i2c_enhance_config *config = dev->config;
1372 struct i2c_enhance_data *data = dev->data;
1373
1374 if (!data->target_attached) {
1375 return -EINVAL;
1376 }
1377
1378 irq_disable(config->i2c_irq_base);
1379
1380 /* Permit to enter power policy and idle mode. */
1381 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1382 if (!config->target_pio_mode) {
1383 chip_permit_idle();
1384 }
1385
1386 data->target_cfg = NULL;
1387 data->target_attached = false;
1388 data->target_nack = 0;
1389
1390 return 0;
1391 }
1392 #endif
1393
1394 static const struct i2c_driver_api i2c_enhance_driver_api = {
1395 .configure = i2c_enhance_configure,
1396 .get_config = i2c_enhance_get_config,
1397 .transfer = i2c_enhance_transfer,
1398 .recover_bus = i2c_enhance_recover_bus,
1399 #ifdef CONFIG_I2C_TARGET
1400 .target_register = i2c_enhance_target_register,
1401 .target_unregister = i2c_enhance_target_unregister,
1402 #endif
1403 };
1404
1405 #ifdef CONFIG_I2C_TARGET
1406 BUILD_ASSERT(IS_ENABLED(CONFIG_I2C_TARGET_BUFFER_MODE),
1407 "When I2C target config is enabled, the buffer mode must be used.");
1408 #endif
1409
1410 #define I2C_ITE_ENHANCE_INIT(inst) \
1411 PINCTRL_DT_INST_DEFINE(inst); \
1412 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1413 50000) || \
1414 (DT_INST_PROP(inst, clock_frequency) == \
1415 I2C_BITRATE_STANDARD) || \
1416 (DT_INST_PROP(inst, clock_frequency) == \
1417 I2C_BITRATE_FAST) || \
1418 (DT_INST_PROP(inst, clock_frequency) == \
1419 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1420 static void i2c_enhance_config_func_##inst(void); \
1421 \
1422 static const struct i2c_enhance_config i2c_enhance_cfg_##inst = { \
1423 .base = (uint8_t *)(DT_INST_REG_ADDR(inst)), \
1424 .irq_config_func = i2c_enhance_config_func_##inst, \
1425 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1426 .i2c_irq_base = DT_INST_IRQN(inst), \
1427 .port = DT_INST_PROP(inst, port_num), \
1428 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1429 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1430 .prescale_scl_low = DT_INST_PROP_OR(inst, prescale_scl_low, 0), \
1431 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1432 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1433 .target_enable = DT_INST_PROP(inst, target_enable), \
1434 .target_pio_mode = DT_INST_PROP(inst, target_pio_mode), \
1435 }; \
1436 \
1437 static struct i2c_enhance_data i2c_enhance_data_##inst; \
1438 \
1439 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_enhance_init, \
1440 NULL, \
1441 &i2c_enhance_data_##inst, \
1442 &i2c_enhance_cfg_##inst, \
1443 POST_KERNEL, \
1444 CONFIG_I2C_INIT_PRIORITY, \
1445 &i2c_enhance_driver_api); \
1446 \
1447 static void i2c_enhance_config_func_##inst(void) \
1448 { \
1449 IRQ_CONNECT(DT_INST_IRQN(inst), \
1450 0, \
1451 i2c_enhance_isr, \
1452 DEVICE_DT_INST_GET(inst), 0); \
1453 }
1454
1455 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_ENHANCE_INIT)
1456
