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Searched refs:csr_write (Results 1 – 9 of 9) sorted by relevance

/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/common/
Dsoc_common_irq.c120 csr_write(mie, 0); in soc_interrupt_init()
121 csr_write(mip, 0); in soc_interrupt_init()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/neorv32/
Dsoc.c15 csr_write(mie, 0); in soc_interrupt_init()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/andes_v5/
Dpma.c78 csr_write(NDS_PMAADDR##x, value); break; in write_pmaaddr_csr()
111 csr_write(NDS_PMACFG##x, pmacfg); break; in write_pmacfg_entry()
/Zephyr-Core-3.5.0/arch/riscv/core/
Dthread.c161 csr_write(mstatus, status); in arch_user_mode_enter()
162 csr_write(mepc, z_thread_entry); in arch_user_mode_enter()
Dsmp.c45 csr_write(mscratch, &_kernel.cpus[cpu_num]); in z_riscv_secondary_cpu_init()
/Zephyr-Core-3.5.0/arch/riscv/include/
Dkernel_arch_func.h33 csr_write(mscratch, &_kernel.cpus[0]); in arch_kernel_init()
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_nuclei_eclic.c176 csr_write(mtvec, ((csr_read(mtvec) & 0xFFFFFFC0) | ECLIC_MODE_MTVEC_Msk)); in nuclei_eclic_init()
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dcsr.h193 #define csr_write(csr, val) \ macro
/Zephyr-Core-3.5.0/tests/kernel/mem_protect/userspace/src/
Dmain.c246 csr_write(pmpaddr3, LLONG_MAX); in ZTEST_USER()
247 csr_write(pmpcfg0, (PMP_R|PMP_W|PMP_X|PMP_NAPOT) << 24); in ZTEST_USER()