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Searched refs:csr_set (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.5.0/arch/riscv/core/
Dfpu.c88 csr_set(mstatus, MSTATUS_FS_INIT); in z_riscv_fpu_load()
115 csr_set(mstatus, MSTATUS_FS_CLEAN); in z_riscv_flush_local_fpu()
316 csr_set(mstatus, _current_cpu->arch.fpu_state); in z_riscv_fpu_thread_context_switch()
Dpmp.c481 csr_set(mstatus, MSTATUS_MPRV); in z_riscv_pmp_stackguard_enable()
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dcsr.h211 #define csr_set(csr, val) \ macro
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_ite_it8xxx2_v2.c241 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
Dintc_ite_it8xxx2.c251 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/
Dsoc.c242 csr_set(mie, MIP_MEIP); in riscv_idle()
/Zephyr-Core-3.5.0/tests/arch/riscv/fpu_sharing/src/
Dmain.c273 csr_set(mstatus, MSTATUS_IEN); in exception_context()