Searched refs:clock_divider (Results 1 – 6 of 6) sorted by relevance
| /Zephyr-Core-3.5.0/drivers/misc/nxp_s32_emios/ |
| D | nxp_s32_emios.c | 53 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, clock_divider), \
58 .clkDivVal = DT_INST_PROP(n, clock_divider) - 1U, \
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| /Zephyr-Core-3.5.0/drivers/can/ |
| D | can_stm32_fdcan.c | 176 uint8_t clock_divider; member
519 if (stm32fd_cfg->clock_divider != 0) { in can_stm32fd_clock_enable()
521 FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1; in can_stm32fd_clock_enable()
664 .clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
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| /Zephyr-Core-3.5.0/drivers/sdhc/ |
| D | intel_emmc_host.c | 220 uint32_t clock_divider; in emmc_clock_set() local
258 clock_divider = (int)(base_freq / (freq * 2)); in emmc_clock_set()
260 LOG_DBG("Clock divider for MMC Clk: %d Hz is %d", speed, clock_divider); in emmc_clock_set()
263 EMMC_HOST_CLK_SDCLCK_FREQ_SEL_MASK, clock_divider); in emmc_clock_set()
265 EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_MASK, clock_divider >> 8); in emmc_clock_set()
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_numaker.c | 343 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_numaker.c | 434 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_numaker.c | 567 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
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