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Searched refs:clock_dev (Results 1 – 25 of 66) sorted by relevance

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/Zephyr-Core-3.5.0/drivers/dac/
Ddac_esp32.c25 const struct device *clock_dev; member
58 if (!cfg->clock_dev) { in dac_esp32_init()
63 if (!device_is_ready(cfg->clock_dev)) { in dac_esp32_init()
68 if (clock_control_on(cfg->clock_dev, in dac_esp32_init()
86 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-Core-3.5.0/tests/drivers/clock_control/nrf_onoff_and_bt/src/
Dmain.c22 static const struct device *const clock_dev = DEVICE_DT_GET_ONE(nordic_nrf_clock); variable
30 zassert_true(device_is_ready(clock_dev)); in setup()
124 check_hf_status(clock_dev, true, true); in ZTEST()
139 check_hf_status(clock_dev, false, true); in ZTEST()
210 check_hf_status(clock_dev, true, false); in ZTEST()
224 check_hf_status(clock_dev, false, true); in ZTEST()
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_mcux_tpm.c29 const struct device *clock_dev; member
145 if (!device_is_ready(config->clock_dev)) { in mcux_tpm_init()
150 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in mcux_tpm_init()
155 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_tpm_init()
192 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_rv32m1_tpm.c28 const struct device *clock_dev; member
144 if (!device_is_ready(config->clock_dev)) { in rv32m1_tpm_init()
149 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in rv32m1_tpm_init()
154 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in rv32m1_tpm_init()
191 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_mcux_sctimer.c27 const struct device *clock_dev; member
85 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_sctimer_pwm_set_cycles()
125 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_sctimer_pwm_get_cycles_per_sec()
182 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_mcux.c25 const struct device *clock_dev; member
79 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_set_cycles()
167 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_get_cycles_per_sec()
184 if (!device_is_ready(config->clock_dev)) { in pwm_mcux_init()
241 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_rcar.c55 const struct device *clock_dev; member
231 ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->mod_clk); in pwm_rcar_init()
236 ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->core_clk, in pwm_rcar_init()
257 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_rv32m1_lpi2c.c26 const struct device *clock_dev; member
85 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_configure()
217 if (!device_is_ready(config->clock_dev)) { in rv32m1_lpi2c_init()
222 err = clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_lpi2c_init()
228 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_init()
268 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
Di2c_mcux_flexcomm.c24 const struct device *clock_dev; member
78 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_flexcomm_configure()
262 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_flexcomm_target_register()
346 if (!device_is_ready(config->clock_dev)) { in mcux_flexcomm_init()
352 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_flexcomm_init()
389 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
Di2c_lpc11u6x.c63 lpc11u6x_i2c_set_bus_speed(cfg, cfg->clock_dev, speed); in lpc11u6x_i2c_configure()
318 if (!device_is_ready(cfg->clock_dev)) { in lpc11u6x_i2c_init()
323 clock_control_on(cfg->clock_dev, (clock_control_subsys_t) cfg->clkid); in lpc11u6x_i2c_init()
326 lpc11u6x_i2c_set_bus_speed(cfg, cfg->clock_dev, 100000); in lpc11u6x_i2c_init()
359 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
/Zephyr-Core-3.5.0/drivers/can/
Dcan_mcux_mcan.c26 const struct device *clock_dev; member
78 return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys, in mcux_mcan_get_core_clock()
89 if (!device_is_ready(mcux_config->clock_dev)) { in mcux_mcan_init()
99 err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys); in mcux_mcan_init()
196 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dcan_esp32_twai.c71 const struct device *clock_dev; member
170 if (!device_is_ready(twai_config->clock_dev)) { in can_esp32_twai_init()
181 err = clock_control_on(twai_config->clock_dev, twai_config->clock_subsys); in can_esp32_twai_init()
272 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_nxp_s32.c21 const struct device *clock_dev; member
89 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); in swt_nxp_s32_install_timeout()
175 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SWT_NODE(n))), \
185 if (!device_is_ready(config->clock_dev)) { \
189 err = clock_control_on(config->clock_dev, config->clock_subsys);\
Dwdt_mcux_wdog.c23 const struct device *clock_dev; member
82 if (!device_is_ready(config->clock_dev)) { in mcux_wdog_install_timeout()
87 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog_install_timeout()
170 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dwdt_esp32.c46 const struct device *clock_dev; member
156 if (!device_is_ready(config->clock_dev)) { in wdt_esp32_init()
161 clock_control_on(config->clock_dev, config->clock_subsys); in wdt_esp32_init()
190 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
Dwdt_mcux_wdog32.c28 const struct device *clock_dev; member
97 if (!device_is_ready(config->clock_dev)) { in mcux_wdog32_install_timeout()
102 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog32_install_timeout()
198 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_rv32m1_intmux.c43 const struct device *clock_dev; member
146 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
157 if (!device_is_ready(config->clock_dev)) { in rv32m1_intmux_init()
162 clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_intmux_init()
/Zephyr-Core-3.5.0/drivers/serial/
Dserial_esp32_usb.c43 const struct device *clock_dev; member
104 if (!device_is_ready(config->clock_dev)) { in serial_esp32_usb_init()
108 int ret = clock_control_on(config->clock_dev, config->clock_subsys); in serial_esp32_usb_init()
268 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Duart_mcux_iuart.c19 const struct device *clock_dev; member
232 if (!device_is_ready(config->clock_dev)) { in mcux_iuart_init()
236 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_iuart_init()
246 clock_control_on(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
265 clock_control_off(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
329 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Duart_mcux.c22 const struct device *clock_dev; member
47 if (!device_is_ready(config->clock_dev)) { in uart_mcux_configure()
51 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in uart_mcux_configure()
352 clock_control_on(config->clock_dev, config->clock_subsys); in uart_mcux_pm_action()
355 clock_control_off(config->clock_dev, config->clock_subsys); in uart_mcux_pm_action()
397 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_rv32m1.c28 const struct device *clock_dev; member
273 if (config->clock_dev) { in gpio_rv32m1_init()
274 if (!device_is_ready(config->clock_dev)) { in gpio_rv32m1_init()
278 ret = clock_control_on(config->clock_dev, config->clock_subsys); in gpio_rv32m1_init()
316 .clock_dev = INST_DT_CLK_CTRL_DEV(n), \
Dgpio_rcar.c32 const struct device *clock_dev; member
243 if (!device_is_ready(config->clock_dev)) { in gpio_rcar_init()
247 ret = clock_control_on(config->clock_dev, in gpio_rcar_init()
289 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_nxp_s32_sys_timer.c39 const struct device *clock_dev; member
153 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) { in nxp_s32_sys_timer_get_frequency()
169 if (!device_is_ready(config->clock_dev)) { in nxp_s32_sys_timer_init()
174 err = clock_control_on(config->clock_dev, config->clock_subsys); in nxp_s32_sys_timer_init()
262 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SYS_TIMER_NODE(n))), \
Dcounter_mcux_gpt.c21 const struct device *clock_dev; member
173 if (!device_is_ready(config->clock_dev)) { in mcux_gpt_init()
178 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_gpt_init()
215 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dcounter_mcux_pit.c25 const struct device *clock_dev; member
125 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) { in mcux_pit_get_frequency()
153 if (!device_is_ready(config->clock_dev)) { in mcux_pit_init()
204 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \

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