Home
last modified time | relevance | path

Searched refs:children_list (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_renesas_cpg_mssr.c188 struct cpg_clk_info_table *children_list = parent->children_list; in rcar_cpg_change_children_in_out_freq() local
190 while (children_list) { in rcar_cpg_change_children_in_out_freq()
191 children_list->in_freq = parent->out_freq; in rcar_cpg_change_children_in_out_freq()
193 if (rcar_cpg_update_out_freq(dev, children_list) < 0) { in rcar_cpg_change_children_in_out_freq()
207 dev->name, children_list->domain, children_list->module); in rcar_cpg_change_children_in_out_freq()
213 rcar_cpg_change_children_in_out_freq(dev, children_list); in rcar_cpg_change_children_in_out_freq()
214 children_list = children_list->next_sibling; in rcar_cpg_change_children_in_out_freq()
393 item->next_sibling = parent->children_list; in rcar_cpg_build_clock_relationship()
394 parent->children_list = item; in rcar_cpg_build_clock_relationship()
Dclock_control_renesas_cpg_mssr.h30 struct cpg_clk_info_table *children_list; member
60 .children_list = NULL, \
74 .children_list = NULL, \