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Searched refs:ch (Results 1 – 25 of 118) sorted by relevance

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/Zephyr-Core-3.5.0/drivers/dma/
Ddma_gd32.c46 #define DMA_CHCTL(dma, ch) REG32((dma + 0x08UL) + 0x14UL * (uint32_t)(ch)) argument
47 #define DMA_CHCNT(dma, ch) REG32((dma + 0x0CUL) + 0x14UL * (uint32_t)(ch)) argument
48 #define DMA_CHPADDR(dma, ch) REG32((dma + 0x10UL) + 0x14UL * (uint32_t)(ch)) argument
49 #define DMA_CHMADDR(dma, ch) REG32((dma + 0x14UL) + 0x14UL * (uint32_t)(ch)) argument
54 #define GD32_DMA_CHCTL(dma, ch) DMA_CHCTL((dma), (ch)) argument
55 #define GD32_DMA_CHCNT(dma, ch) DMA_CHCNT((dma), (ch)) argument
56 #define GD32_DMA_CHPADDR(dma, ch) DMA_CHPADDR((dma), (ch)) argument
57 #define GD32_DMA_CHMADDR(dma, ch) DMA_CHMADDR((dma), (ch)) argument
95 gd32_dma_periph_increase_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_periph_increase_enable() argument
97 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_PNAGA; in gd32_dma_periph_increase_enable()
[all …]
Ddma_rpi_pico.c58 ((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl &= ~DMA_INT_ERROR_FLAGS; in rpi_pico_dma_channel_clear_error_flags()
66 return ((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl & DMA_INT_ERROR_FLAGS; in rpi_pico_dma_channel_get_error_flags()
201 static int dma_rpi_pico_reload(const struct device *dev, uint32_t ch, uint32_t src, uint32_t dst, in dma_rpi_pico_reload() argument
207 if (ch >= cfg->channels) { in dma_rpi_pico_reload()
208 LOG_ERR("reload channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, ch); in dma_rpi_pico_reload()
212 if (dma_channel_is_busy(ch)) { in dma_rpi_pico_reload()
216 data->channels[ch].source_address = (void *)src; in dma_rpi_pico_reload()
217 data->channels[ch].dest_address = (void *)dst; in dma_rpi_pico_reload()
218 data->channels[ch].block_size = size; in dma_rpi_pico_reload()
219 dma_channel_configure(ch, &data->channels[ch].config, data->channels[ch].dest_address, in dma_rpi_pico_reload()
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/Zephyr-Core-3.5.0/subsys/settings/src/
Dsettings.c43 STRUCT_SECTION_FOREACH(settings_handler_static, ch) { in settings_register()
44 if (strcmp(handler->name, ch->name) == 0) { in settings_register()
51 struct settings_handler *ch; in settings_register() local
52 SYS_SLIST_FOR_EACH_CONTAINER(&settings_handlers, ch, node) { in settings_register()
53 if (strcmp(handler->name, ch->name) == 0) { in settings_register()
148 STRUCT_SECTION_FOREACH(settings_handler_static, ch) { in settings_parse_and_lookup()
149 if (!settings_name_steq(name, ch->name, &tmpnext)) { in settings_parse_and_lookup()
153 bestmatch = ch; in settings_parse_and_lookup()
159 if (settings_name_steq(ch->name, bestmatch->name, NULL)) { in settings_parse_and_lookup()
160 bestmatch = ch; in settings_parse_and_lookup()
[all …]
Dsettings_runtime.c28 struct settings_handler_static *ch; in settings_runtime_set() local
32 ch = settings_parse_and_lookup(name, &name_key); in settings_runtime_set()
33 if (!ch) { in settings_runtime_set()
39 return ch->h_set(name_key, len, settings_runtime_read_cb, (void *)&arg); in settings_runtime_set()
44 struct settings_handler_static *ch; in settings_runtime_get() local
47 ch = settings_parse_and_lookup(name, &name_key); in settings_runtime_get()
48 if (!ch) { in settings_runtime_get()
52 if (!ch->h_get) { in settings_runtime_get()
56 return ch->h_get(name_key, data, len); in settings_runtime_get()
61 struct settings_handler_static *ch; in settings_runtime_commit() local
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Dsettings_store.c134 STRUCT_SECTION_FOREACH(settings_handler_static, ch) { in settings_save()
135 if (ch->h_export) { in settings_save()
136 rc2 = ch->h_export(settings_save_one); in settings_save()
144 struct settings_handler *ch; in settings_save() local
145 SYS_SLIST_FOR_EACH_CONTAINER(&settings_handlers, ch, node) { in settings_save()
146 if (ch->h_export) { in settings_save()
147 rc2 = ch->h_export(settings_save_one); in settings_save()
/Zephyr-Core-3.5.0/subsys/net/lib/http/
Dhttp_parser_url.c147 enum state parse_url_char(enum state s, const char ch) in parse_url_char() argument
149 if (ch == ' ' || ch == '\r' || ch == '\n') { in parse_url_char()
154 if (ch == '\t' || ch == '\f') { in parse_url_char()
166 if (ch == '/' || ch == '*') { in parse_url_char()
170 if (IS_ALPHA(ch)) { in parse_url_char()
177 if (IS_ALPHA(ch)) { in parse_url_char()
181 if (ch == ':') { in parse_url_char()
188 if (ch == '/') { in parse_url_char()
195 if (ch == '/') { in parse_url_char()
202 if (ch == '@') { in parse_url_char()
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Dhttp_parser.c295 #define IS_HEADER_CHAR(ch) \ argument
296 (ch == CR || ch == LF || ch == 9 || \
297 ((unsigned char)ch > 31 && ch != 127))
370 int parser_header_state(struct http_parser *parser, char ch, char c) in parser_header_state() argument
467 if (ch != ' ') { in parser_header_state()
482 enum header_states *header_state, char ch, char c) in header_states() argument
522 if (ch == ' ') { in header_states()
526 if (UNLIKELY(!IS_NUM(ch))) { in header_states()
534 t += ch - '0'; in header_states()
612 if (ch == ',') { in header_states()
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/Zephyr-Core-3.5.0/tests/drivers/build_all/sensor/src/
Dgeneric_test.c106 for (enum sensor_channel ch = 0; ch < ARRAY_SIZE(channel_table); ch++) { in run_generic_test() local
107 if (SENSOR_CHANNEL_3_AXIS(ch)) { in run_generic_test()
114 if (emul_sensor_backend_get_sample_range(emul, ch, &lower, &upper, in run_generic_test()
115 &channel_table[ch].epsilon, &shift) == 0) { in run_generic_test()
117 channel_table[ch].supported = true; in run_generic_test()
119 LOG_INF("CH %d: lower=%d, upper=%d, eps=%d, shift=%d", ch, lower, upper, in run_generic_test()
120 channel_table[ch].epsilon, shift); in run_generic_test()
123 iodev_all_channels[iodev_read_config.count++] = ch; in run_generic_test()
129 channel_table[ch].expected_value_shift = shift; in run_generic_test()
131 channel_table[ch].expected_values[i] = in run_generic_test()
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/Zephyr-Core-3.5.0/soc/arm/nordic_nrf/nrf53/
Dsync_rtc.c34 } ch; member
76 nrf_ipc_event_t ipc_evt = nrf_ipc_receive_event_get(channels.ch.ipc_in); in ppi_ipc_to_rtc()
77 uint32_t task_addr = z_nrf_rtc_timer_capture_task_address_get(channels.ch.rtc); in ppi_ipc_to_rtc()
80 nrfx_gppi_task_endpoint_setup(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
81 nrf_ipc_publish_set(NRF_IPC, ipc_evt, channels.ch.ppi); in ppi_ipc_to_rtc()
83 nrfx_gppi_task_endpoint_clear(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
95 uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc); in ppi_rtc_to_ipc()
96 nrf_ipc_task_t ipc_task = nrf_ipc_send_task_get(channels.ch.ipc_out); in ppi_rtc_to_ipc()
99 nrf_ipc_subscribe_set(NRF_IPC, ipc_task, channels.ch.ppi); in ppi_rtc_to_ipc()
100 nrfx_gppi_event_endpoint_setup(channels.ch.ppi, evt_addr); in ppi_rtc_to_ipc()
[all …]
/Zephyr-Core-3.5.0/drivers/mbox/
Dmbox_andes_plic_sw.c63 static inline bool is_channel_valid(const struct device *dev, uint32_t ch) in is_channel_valid() argument
67 return (ch <= conf->channel_max); in is_channel_valid()
70 static int mbox_andes_send(const struct device *dev, uint32_t ch, in mbox_andes_send() argument
77 if (!is_channel_valid(dev, ch)) { in mbox_andes_send()
82 plic_sw_irq_set_pending(dev, ch + 1); in mbox_andes_send()
87 static int mbox_andes_register_callback(const struct device *dev, uint32_t ch, in mbox_andes_register_callback() argument
96 if (ch > conf->channel_max) { in mbox_andes_register_callback()
102 if (ch & data->ipi_channel & data->reg_cb_channel) { in mbox_andes_register_callback()
107 data->reg_cb_channel |= BIT(ch); in mbox_andes_register_callback()
109 data->cb[ch] = cb; in mbox_andes_register_callback()
[all …]
Dmbox_nrfx_ipc.c34 static inline bool is_rx_channel_valid(const struct device *dev, uint32_t ch) in is_rx_channel_valid() argument
38 return ((ch < IPC_CONF_NUM) && (conf->rx_mask & BIT(ch))); in is_rx_channel_valid()
41 static inline bool is_tx_channel_valid(const struct device *dev, uint32_t ch) in is_tx_channel_valid() argument
45 return ((ch < IPC_CONF_NUM) && (conf->tx_mask & BIT(ch))); in is_tx_channel_valid()
164 for (size_t ch = 0; ch < IPC_CONF_NUM; ch++) { in enable_dt_channels() local
165 if (conf->tx_mask & BIT(ch)) { in enable_dt_channels()
166 ch_config.send_task_config[ch] = BIT(ch); in enable_dt_channels()
169 if (conf->rx_mask & BIT(ch)) { in enable_dt_channels()
170 ch_config.receive_event_config[ch] = BIT(ch); in enable_dt_channels()
/Zephyr-Core-3.5.0/drivers/ipm/
Dipm_stm32_ipcc.c38 #define IPCC_EnableReceiveChannel(hipcc, ch) \ argument
39 LL_C1_IPCC_EnableReceiveChannel(hipcc, 1 << ch)
40 #define IPCC_EnableTransmitChannel(hipcc, ch) \ argument
41 LL_C1_IPCC_EnableTransmitChannel(hipcc, 1 << ch)
42 #define IPCC_DisableReceiveChannel(hipcc, ch) \ argument
43 LL_C2_IPCC_DisableReceiveChannel(hipcc, 1 << ch)
44 #define IPCC_DisableTransmitChannel(hipcc, ch) \ argument
45 LL_C1_IPCC_DisableTransmitChannel(hipcc, 1 << ch)
47 #define IPCC_ClearFlag_CHx(hipcc, ch) LL_C1_IPCC_ClearFlag_CHx(hipcc, 1 << ch) argument
48 #define IPCC_SetFlag_CHx(hipcc, ch) LL_C1_IPCC_SetFlag_CHx(hipcc, 1 << ch) argument
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/Zephyr-Core-3.5.0/dts/arm/cypress/
Dpsoc6_cm0.dtsi30 compatible = "cypress,psoc6-intmux-ch";
38 compatible = "cypress,psoc6-intmux-ch";
46 compatible = "cypress,psoc6-intmux-ch";
54 compatible = "cypress,psoc6-intmux-ch";
62 compatible = "cypress,psoc6-intmux-ch";
70 compatible = "cypress,psoc6-intmux-ch";
78 compatible = "cypress,psoc6-intmux-ch";
86 compatible = "cypress,psoc6-intmux-ch";
94 compatible = "cypress,psoc6-intmux-ch";
102 compatible = "cypress,psoc6-intmux-ch";
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/Zephyr-Core-3.5.0/subsys/debug/gdbstub/
Dgdbstub_backend_serial.c36 void z_gdb_putchar(unsigned char ch) in z_gdb_putchar() argument
38 uart_poll_out(uart_dev, ch); in z_gdb_putchar()
43 unsigned char ch; in z_gdb_getchar() local
45 while (uart_poll_in(uart_dev, &ch) < 0) { in z_gdb_getchar()
48 return ch; in z_gdb_getchar()
/Zephyr-Core-3.5.0/drivers/adc/
Dadc_cc32xx.c67 static inline void start_sampling(unsigned long base, int ch) in start_sampling() argument
69 MAP_ADCChannelEnable(base, ch); in start_sampling()
71 while (!MAP_ADCFIFOLvlGet(base, ch)) { in start_sampling()
73 MAP_ADCFIFORead(base, ch); in start_sampling()
75 MAP_ADCIntClear(base, ch, ISR_MASK); in start_sampling()
76 MAP_ADCIntEnable(base, ch, ISR_MASK); in start_sampling()
118 const int ch = s_channel[i]; in adc_cc32xx_init() local
120 MAP_ADCIntDisable(config->base, ch, ISR_MASK); in adc_cc32xx_init()
121 MAP_ADCChannelDisable(config->base, ch); in adc_cc32xx_init()
122 MAP_ADCDMADisable(config->base, ch); in adc_cc32xx_init()
[all …]
Dadc_ite_it8xxx2.c38 #define ADC_CHANNEL_OFFSET(ch) ((ch)-CHIP_ADC_CH13-ADC_CHANNEL_SHIFT) argument
67 uint32_t ch; member
125 static void adc_disable_measurement(uint32_t ch) in adc_disable_measurement() argument
129 if (ch <= CHIP_ADC_CH7) { in adc_disable_measurement()
142 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(ch)].VCHCTL = in adc_disable_measurement()
158 return (data->ch <= CHIP_ADC_CH7) ? in adc_data_valid()
160 (adc_regs->ADCDVSTS2 & BIT(ADC_CHANNEL_OFFSET(data->ch))); in adc_data_valid()
170 if (data->ch <= CHIP_ADC_CH7) { in adc_it8xxx2_get_sample()
177 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATM << 8 | in adc_it8xxx2_get_sample()
178 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATL; in adc_it8xxx2_get_sample()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/
Demul_sensor.h29 int (*set_channel)(const struct emul *target, enum sensor_channel ch, q31_t value,
32 int (*get_sample_range)(const struct emul *target, enum sensor_channel ch, q31_t *lower,
63 static inline int emul_sensor_backend_set_channel(const struct emul *target, enum sensor_channel ch, in emul_sensor_backend_set_channel() argument
73 return api->set_channel(target, ch, value, shift); in emul_sensor_backend_set_channel()
96 enum sensor_channel ch, q31_t *lower, in emul_sensor_backend_get_sample_range() argument
106 return api->get_sample_range(target, ch, lower, upper, epsilon, shift); in emul_sensor_backend_get_sample_range()
/Zephyr-Core-3.5.0/modules/lvgl/
Dlvgl_display_24bit.c39 mix_color.ch.red = *buf_xy; in lvgl_set_px_cb_24bit()
40 mix_color.ch.green = *(buf_xy + 1); in lvgl_set_px_cb_24bit()
41 mix_color.ch.blue = *(buf_xy + 2); in lvgl_set_px_cb_24bit()
47 *buf_xy = converted_color.ch.red; in lvgl_set_px_cb_24bit()
48 *(buf_xy + 1) = converted_color.ch.green; in lvgl_set_px_cb_24bit()
49 *(buf_xy + 2) = converted_color.ch.blue; in lvgl_set_px_cb_24bit()
/Zephyr-Core-3.5.0/drivers/sensor/fdc2x1x/
Dfdc2x1x.c31 uint8_t ch, double *freq) in fdc2x1x_raw_to_freq() argument
38 data->channel_buf[ch]) / pow(2, 28); in fdc2x1x_raw_to_freq()
41 ((data->channel_buf[ch] / pow(2, 12 + cfg->output_gain)) + in fdc2x1x_raw_to_freq()
42 (cfg->ch_cfg[ch].offset / pow(2, 16))); in fdc2x1x_raw_to_freq()
55 uint8_t ch, double freq, double *capacitance) in fdc2x1x_raw_to_capacitance() argument
315 static int fdc2x1x_set_active_channel(const struct device *dev, uint8_t ch) in fdc2x1x_set_active_channel() argument
320 FDC2X1X_CFG_ACTIVE_CHAN_SET(ch)); in fdc2x1x_set_active_channel()
733 int ch; in fdc2x1x_init_config() local
738 for (ch = 0; ch < cfg->num_channels; ch++) { in fdc2x1x_init_config()
739 ret = fdc2x1x_set_fin_sel(dev, ch, cfg->ch_cfg[ch].fin_sel); in fdc2x1x_init_config()
[all …]
/Zephyr-Core-3.5.0/subsys/bluetooth/host/
Dl2cap.c178 void bt_l2cap_chan_remove(struct bt_conn *conn, struct bt_l2cap_chan *ch) in bt_l2cap_chan_remove() argument
184 if (chan == ch) { in bt_l2cap_chan_remove()
318 struct bt_l2cap_le_chan *ch = CHAN_RX(work); in l2cap_rx_process() local
321 while ((buf = net_buf_get(&ch->rx_queue, K_NO_WAIT))) { in l2cap_rx_process()
322 LOG_DBG("ch %p buf %p", ch, buf); in l2cap_rx_process()
323 l2cap_chan_le_recv(ch, buf); in l2cap_rx_process()
493 static int l2cap_le_conn_req(struct bt_l2cap_le_chan *ch) in l2cap_le_conn_req() argument
498 ch->ident = get_ident(); in l2cap_le_conn_req()
501 ch->ident, sizeof(*req)); in l2cap_le_conn_req()
507 req->psm = sys_cpu_to_le16(ch->psm); in l2cap_le_conn_req()
[all …]
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_nrfx_common.c16 uint8_t ch; in spi_nrfx_wake_init() local
19 .p_in_channel = &ch, in spi_nrfx_wake_init()
23 res = nrfx_gpiote_channel_alloc(&ch); in spi_nrfx_wake_init()
33 nrfx_gpiote_channel_free(ch); in spi_nrfx_wake_init()
/Zephyr-Core-3.5.0/subsys/bluetooth/shell/
Dl2cap.c53 struct bt_l2cap_le_chan ch; member
55 #define L2CH_CHAN(_chan) CONTAINER_OF(_chan, struct l2ch, ch.chan)
58 #define L2CAP_CHAN(_chan) _chan->ch.chan
93 bt_l2cap_chan_recv_complete(&c->ch.chan, buf); in l2cap_recv_cb()
172 .ch.chan.ops = &l2cap_ops,
173 .ch.rx.mtu = DATA_MTU,
227 if (l2ch_chan.ch.chan.conn) { in l2cap_accept()
232 *chan = &l2ch_chan.ch.chan; in l2cap_accept()
283 struct bt_l2cap_chan *l2cap_ecred_chans[] = { &l2ch_chan.ch.chan, NULL }; in cmd_ecred_reconfigure()
292 if (!l2ch_chan.ch.chan.conn) { in cmd_ecred_reconfigure()
[all …]
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_ite_it8xxx2.c50 int ch = config->channel; in pwm_enable() local
54 *reg_pcsgr &= ~BIT(ch); in pwm_enable()
57 *reg_pcsgr |= BIT(ch); in pwm_enable()
97 int ch = config->channel; in pwm_it8xxx2_set_cycles() local
104 *reg_pwmpol |= BIT(ch); in pwm_it8xxx2_set_cycles()
106 *reg_pwmpol &= ~BIT(ch); in pwm_it8xxx2_set_cycles()
111 inst->PWMODENR |= BIT(ch); in pwm_it8xxx2_set_cycles()
218 int ch = config->channel; in pwm_it8xxx2_init() local
231 pcssg_shift = (ch % 4) * 2; in pwm_it8xxx2_init()
Dpwm_rpi_pico.c57 static int pwm_rpi_get_cycles_per_sec(const struct device *dev, uint32_t ch, uint64_t *cycles) in pwm_rpi_get_cycles_per_sec() argument
60 int slice = pwm_rpi_channel_to_slice(ch); in pwm_rpi_get_cycles_per_sec()
62 if (ch >= PWM_RPI_NUM_CHANNELS) { in pwm_rpi_get_cycles_per_sec()
96 static int pwm_rpi_set_cycles(const struct device *dev, uint32_t ch, uint32_t period_cycles, in pwm_rpi_set_cycles() argument
99 if (ch >= PWM_RPI_NUM_CHANNELS) { in pwm_rpi_set_cycles()
108 int slice = pwm_rpi_channel_to_slice(ch); in pwm_rpi_set_cycles()
111 int pico_channel = pwm_rpi_channel_to_pico_channel(ch); in pwm_rpi_set_cycles()
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/
Dgdbstub.py41 ch = socket.recv(1)
42 if ch == b'$':
47 ch = socket.recv(1)
48 if ch == b'#':
52 checksum += ord(ch)
53 data += ch
56 ch = socket.recv(2)
57 in_chksum = ord(binascii.unhexlify(ch))

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