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/Zephyr-Core-3.5.0/drivers/can/
Dcan_stm32_fdcan.c261 uint32_t bits; in can_stm32fd_read_reg() local
269 err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits); in can_stm32fd_read_reg()
279 *val |= FIELD_PREP(CAN_MCAN_IR_ARA, FIELD_GET(CAN_STM32FD_IR_ARA, bits)); in can_stm32fd_read_reg()
280 *val |= FIELD_PREP(CAN_MCAN_IR_PED, FIELD_GET(CAN_STM32FD_IR_PED, bits)); in can_stm32fd_read_reg()
281 *val |= FIELD_PREP(CAN_MCAN_IR_PEA, FIELD_GET(CAN_STM32FD_IR_PEA, bits)); in can_stm32fd_read_reg()
282 *val |= FIELD_PREP(CAN_MCAN_IR_WDI, FIELD_GET(CAN_STM32FD_IR_WDI, bits)); in can_stm32fd_read_reg()
283 *val |= FIELD_PREP(CAN_MCAN_IR_BO, FIELD_GET(CAN_STM32FD_IR_BO, bits)); in can_stm32fd_read_reg()
284 *val |= FIELD_PREP(CAN_MCAN_IR_EW, FIELD_GET(CAN_STM32FD_IR_EW, bits)); in can_stm32fd_read_reg()
285 *val |= FIELD_PREP(CAN_MCAN_IR_EP, FIELD_GET(CAN_STM32FD_IR_EP, bits)); in can_stm32fd_read_reg()
286 *val |= FIELD_PREP(CAN_MCAN_IR_ELO, FIELD_GET(CAN_STM32FD_IR_ELO, bits)); in can_stm32fd_read_reg()
[all …]
/Zephyr-Core-3.5.0/samples/drivers/lcd_hd44780/src/
Dmain.c194 void _pi_lcd_4bits_wr(const struct device *gpio_dev, uint8_t bits) in _pi_lcd_4bits_wr() argument
201 if ((bits & BIT(4)) == BIT(4)) { in _pi_lcd_4bits_wr()
204 if ((bits & BIT(5)) == BIT(5)) { in _pi_lcd_4bits_wr()
207 if ((bits & BIT(6)) == BIT(6)) { in _pi_lcd_4bits_wr()
210 if ((bits & BIT(7)) == BIT(7)) { in _pi_lcd_4bits_wr()
222 if ((bits & BIT(0)) == BIT(0)) { in _pi_lcd_4bits_wr()
225 if ((bits & BIT(1)) == BIT(1)) { in _pi_lcd_4bits_wr()
228 if ((bits & BIT(2)) == BIT(2)) { in _pi_lcd_4bits_wr()
231 if ((bits & BIT(3)) == BIT(3)) { in _pi_lcd_4bits_wr()
239 void _pi_lcd_8bits_wr(const struct device *gpio_dev, uint8_t bits) in _pi_lcd_8bits_wr() argument
[all …]
/Zephyr-Core-3.5.0/arch/arc/core/mpu/
Darc_mpu_v2_internal.h57 uint8_t bits = find_msb_set(size) - 1; in _region_init() local
59 if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) { in _region_init()
60 bits = ARC_FEATURE_MPU_ALIGNMENT_BITS; in _region_init()
63 if (BIT(bits) < size) { in _region_init()
64 bits++; in _region_init()
68 region_attr |= AUX_MPU_RDP_REGION_SIZE(bits); in _region_init()
Darc_mpu_v6_internal.h83 uint8_t bits = find_msb_set(size) - 1; in _region_init() local
85 if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) { in _region_init()
86 bits = ARC_FEATURE_MPU_ALIGNMENT_BITS; in _region_init()
89 if (BIT(bits) < size) { in _region_init()
90 bits++; in _region_init()
101 region_attr |= AUX_MPU_RDP_REGION_SIZE(bits) | AUX_MPU_RDB_NV; in _region_init()
/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_dw.c216 rx_buffer_depth = ic_comp_param_1.bits.rx_buffer_depth + 1; in i2c_dw_data_ask()
217 tx_buffer_depth = ic_comp_param_1.bits.tx_buffer_depth + 1; in i2c_dw_data_ask()
408 if (intr_stat.bits.rx_full) { in i2c_dw_isr()
421 if (intr_stat.bits.tx_empty) { in i2c_dw_isr()
441 if (intr_stat.bits.stop_det) { in i2c_dw_isr()
454 if (intr_stat.bits.rx_full) { in i2c_dw_isr()
467 if (intr_stat.bits.rd_req) { in i2c_dw_isr()
516 ic_con.bits.master_mode = 1U; in i2c_dw_setup()
517 ic_con.bits.slave_disable = 1U; in i2c_dw_setup()
522 ic_con.bits.restart_en = 1U; in i2c_dw_setup()
[all …]
Di2c_dw_registers.h28 } bits; member
87 } bits; member
99 } bits; member
115 } bits; member
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_sam0_eic.c54 uint16_t bits = EIC->INTFLAG.reg; in sam0_eic_isr() local
58 EIC->INTFLAG.reg = bits; in sam0_eic_isr()
62 line_index = __CLZ(__RBIT(bits)); in sam0_eic_isr()
63 bits >>= line_index; in sam0_eic_isr()
65 if (bits & 0xFF) { in sam0_eic_isr()
69 bits >>= 8; in sam0_eic_isr()
77 for (; bits; bits >>= 1, line_index++) { in sam0_eic_isr()
78 if (!(bits & 1)) { in sam0_eic_isr()
Dintc_intel_vtd.c355 irte.bits.vector = vector; in vtd_ictl_remap()
359 irte.bits.dst_id = x86_read_loapic(LOAPIC_LDR); in vtd_ictl_remap()
362 irte.bits.dst_id = 0xFF << 8; in vtd_ictl_remap()
367 irte.bits.src_validation_type = 1; in vtd_ictl_remap()
368 irte.bits.src_id = src_id; in vtd_ictl_remap()
377 irte.bits.trigger_mode = (flags & IOAPIC_TRIGGER_MASK) >> 15; in vtd_ictl_remap()
378 irte.bits.delivery_mode = delivery_mode >> 8; in vtd_ictl_remap()
379 irte.bits.redirection_hint = 1; in vtd_ictl_remap()
380 irte.bits.dst_mode = 1; /* Always logical */ in vtd_ictl_remap()
381 irte.bits.present = 1; in vtd_ictl_remap()
DKconfig.multilevel22 int "Total number of first level interrupt bits"
26 The number of bits to use of the 32 bit interrupt mask for first
65 int "Total number of second level interrupt bits"
69 The number of bits to use of the 32 bit interrupt mask for second
119 int "Total number of third level interrupt bits"
123 The number of bits to use of the 32 bit interrupt mask for third
/Zephyr-Core-3.5.0/subsys/usb/device_next/class/
Dusbd_msc.c121 atomic_t bits; member
171 if (atomic_test_and_set_bit(&ctx->bits, MSC_BULK_OUT_QUEUED)) { in msc_queue_bulk_out_ep()
188 atomic_clear_bit(&ctx->bits, MSC_BULK_OUT_QUEUED); in msc_queue_bulk_out_ep()
219 atomic_clear_bit(&ctx->bits, MSC_BULK_IN_WEDGED); in msc_reset_handler()
220 atomic_clear_bit(&ctx->bits, MSC_BULK_OUT_WEDGED); in msc_reset_handler()
258 if (atomic_test_and_set_bit(&ctx->bits, MSC_BULK_IN_QUEUED)) { in msc_process_read()
298 atomic_clear_bit(&ctx->bits, MSC_BULK_IN_QUEUED); in msc_process_read()
486 atomic_set_bit(&ctx->bits, MSC_BULK_IN_WEDGED); in msc_handle_bulk_out()
487 atomic_set_bit(&ctx->bits, MSC_BULK_OUT_WEDGED); in msc_handle_bulk_out()
532 if (atomic_test_and_set_bit(&ctx->bits, MSC_BULK_IN_QUEUED)) { in msc_send_csw()
[all …]
/Zephyr-Core-3.5.0/drivers/power_domain/
Dpower_domain_intel_adsp.c20 static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enable) in pd_intel_adsp_set_power_enable() argument
22 uint16_t SPA_bit_mask = BIT(bits->SPA_bit); in pd_intel_adsp_set_power_enable()
28 if (!WAIT_FOR(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrsts) & BIT(bits->CPA_bit), in pd_intel_adsp_set_power_enable()
/Zephyr-Core-3.5.0/doc/build/version/
Dindex.rst79 | APPVERSION | Numerical | ``VERSION_MAJOR`` (left shifted by 24 bits), |br| | 0…
80 | | | ``VERSION_MINOR`` (left shifted by 16 bits), |br| | …
81 | | | ``PATCHLEVEL`` (left shifted by 8 bits), |br| | …
84 | APP_VERSION_NUMBER | Numerical | ``VERSION_MAJOR`` (left shifted by 16 bits), |br| | 0…
85 | | | ``VERSION_MINOR`` (left shifted by 8 bits), |br| | …
133 | APPVERSION | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 24 bits), |br| | 0x1020…
134 | | | ``VERSION_MINOR`` (left shifted by 16 bits), |br| | …
135 | | | ``PATCHLEVEL`` (left shifted by 8 bits), |br| | …
138 | APP_VERSION_NUMBER | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 16 bits), |br| | 0x1020…
139 | | | ``VERSION_MINOR`` (left shifted by 8 bits), |br| | …
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_bitbang.c19 int bits; member
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure() local
47 if (bits > 16) { in spi_bitbang_configure()
52 data->bits = bits; in spi_bitbang_configure()
53 data->dfs = ((data->bits - 1) / 8) + 1; in spi_bitbang_configure()
159 int shift = data->bits - 1; in spi_bitbang_transceive()
Dspi_rpi_pico_pio.c111 uint32_t bits; in spi_pico_pio_configure() local
137 bits = SPI_WORD_SIZE_GET(spi_cfg->operation); in spi_pico_pio_configure()
139 if (bits != 8) { in spi_pico_pio_configure()
144 data->dfs = DIV_ROUND_UP(bits, 8); in spi_pico_pio_configure()
202 sm_config_set_in_shift(&sm_config, false, true, bits); in spi_pico_pio_configure()
204 sm_config_set_out_shift(&sm_config, false, true, bits); in spi_pico_pio_configure()
/Zephyr-Core-3.5.0/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/
Dcyabs_rtos_zephyr.c527 cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) in cy_rtos_setbits_event() argument
537 k_event_post(event, bits); in cy_rtos_setbits_event()
543 cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) in cy_rtos_clearbits_event() argument
558 k_event_set(event, (~bits & current_bits)); in cy_rtos_clearbits_event()
564 cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) in cy_rtos_getbits_event() argument
568 if ((event == NULL) || (bits == NULL)) { in cy_rtos_getbits_event()
574 *bits = event->events; in cy_rtos_getbits_event()
580 cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, in cy_rtos_waitbits_event() argument
585 if ((event == NULL) || (bits == NULL)) { in cy_rtos_waitbits_event()
588 uint32_t wait_for = *bits; in cy_rtos_waitbits_event()
[all …]
/Zephyr-Core-3.5.0/tests/arch/x86/info/src/
Dacpi.c47 printk("Info: Bus: %d, dev:%d, fun:%d\n", dmar_id[i].bits.bus, in vtd_dev_scope_info()
48 dmar_id[i].bits.device, dmar_id[i].bits.function); in vtd_dev_scope_info()
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_dwmac_stm32h7x.c37 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
41 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits),
45 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits),
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/
DKconfig.df278 bool "Conversion of IQ samples to 8 bits wide by 4 bits shift"
282 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
284 8 bits by ordinary right shift operation by 4 bits. That means there is loss in accuracy
288 bool "Conversion of IQ samples to 8 bits wide by 2 bits shift"
292 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
294 8 bits by ordinary right shift operation by 2 bits and a cast to int8_t. That means there
299 bool "Conversion of IQ samples to 8 bits wide by use of 8 LSB"
303 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
305 8 bits by use of 8 least significant bits. This conversion may be used only if you are
306 sure actual samples are not greater than 8 bits. This prevents additional accuracy loss
[all …]
/Zephyr-Core-3.5.0/drivers/timer/
DKconfig.cortex_m_systick34 This driver, due to its limited 24-bits hardware counter, is already
36 count a 64-bits value to support sys_clock_cycle_get_64().
39 32 bits.
/Zephyr-Core-3.5.0/tests/drivers/uart/uart_mix_fifo_poll/
DREADME.txt13 following: 4 MSB bits contains stream ID, 4 LSB bits are incremented.
/Zephyr-Core-3.5.0/boards/arm64/mimx93_evk/
Dmimx93_evk_a55_sof_defconfig10 # The number of bits used for PAs and VAs
12 # bits used for said address used by Jailhouse.
/Zephyr-Core-3.5.0/subsys/testsuite/ztest/src/
Dztest_mock.c80 #define DEFINE_BITFIELD(name, bits) \ argument
81 unsigned long(name)[DIV_ROUND_UP(bits, BITS_PER_UL)]
84 const unsigned int bits) in sys_bitfield_find_first_clear() argument
86 const size_t words = DIV_ROUND_UP(bits, BITS_PER_UL); in sys_bitfield_find_first_clear()
106 if (bit < bits) { in sys_bitfield_find_first_clear()
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/util/
Dutil.c231 uint8_t bits; in util_saa_le32() local
270 bits = find_msb_set(CONFIG_BT_CTLR_ADV_ISO_SET * 0x03); in util_saa_le32()
271 saa &= ~BIT_MASK(bits); in util_saa_le32()
/Zephyr-Core-3.5.0/boards/arm/arty/dts/
Darty_a7_arm_designstart.dtsi180 xlnx,num-ss-bits = <0x1>;
181 xlnx,num-transfer-bits = <0x8>;
192 xlnx,num-ss-bits = <0x1>;
193 xlnx,num-transfer-bits = <0x8>;
261 xlnx,num-ss-bits = <0x1>;
262 xlnx,num-transfer-bits = <0x8>;
/Zephyr-Core-3.5.0/dts/arm/nordic/
Dnrf91_peripherals.dtsi161 easydma-maxcnt-bits = <13>;
177 easydma-maxcnt-bits = <13>;
193 easydma-maxcnt-bits = <13>;
209 easydma-maxcnt-bits = <13>;
225 easydma-maxcnt-bits = <13>;
241 easydma-maxcnt-bits = <13>;
257 easydma-maxcnt-bits = <13>;
273 easydma-maxcnt-bits = <13>;

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