Searched refs:bank_idx (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-Core-3.5.0/drivers/memc/ |
| D | memc_stm32_nor_psram.c | 92 size_t bank_idx; in memc_stm32_nor_psram_init() local
95 for (bank_idx = 0U; bank_idx < config->banks_len; ++bank_idx) { in memc_stm32_nor_psram_init()
96 memory_type = config->banks[bank_idx].init.MemoryType; in memc_stm32_nor_psram_init()
100 ret = memc_stm32_nor_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
105 ret = memc_stm32_psram_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
115 memory_type, config->banks[bank_idx].init.NSBank, ret); in memc_stm32_nor_psram_init()
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| /Zephyr-Core-3.5.0/drivers/mm/ |
| D | mm_drv_intel_adsp_mtl_tlb.c | 135 static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking) in sys_mm_drv_hpsram_pwr() argument
138 if (bank_idx > ace_hpsram_get_bank_count()) { in sys_mm_drv_hpsram_pwr()
142 HPSRAM_REGS(bank_idx)->HSxPGCTL = !enable; in sys_mm_drv_hpsram_pwr()
145 while (HPSRAM_REGS(bank_idx)->HSxPGISTS == enable) { in sys_mm_drv_hpsram_pwr()
171 uint32_t entry_idx, bank_idx; in sys_mm_drv_map_page() local
241 bank_idx = get_hpsram_bank_idx(pa); in sys_mm_drv_map_page()
242 if (sys_mm_drv_bank_page_mapped(&hpsram_bank[bank_idx]) == 1) { in sys_mm_drv_map_page()
243 sys_mm_drv_hpsram_pwr(bank_idx, true, false); in sys_mm_drv_map_page()
333 uint32_t entry_idx, bank_idx; in sys_mm_drv_unmap_page() local
378 bank_idx = get_hpsram_bank_idx(pa); in sys_mm_drv_unmap_page()
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