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/Zephyr-Core-3.5.0/arch/xtensa/core/
Dcrt1.S48 # define ARG3 a8 /* 3rd outgoing call argument */
171 .L0zte: l32i a8, a6, 0 /* get start address, assumed multiple of 4 */
174 sub a10, a9, a8 /* a10 = length, assumed a multiple of 4 */
176 s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
177 addi a8, a8, 4
179 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
180 s32i a0, a8, 4
181 addi a8, a8, 8
184 s32i a0, a8, 0 /* clear 16 bytes at a time... */
185 s32i a0, a8, 4
[all …]
Dwindow_vectors.S113 _bbci.l a8, 30, _WindowUnderflow8
201 s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */
234 l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */
Dcoredump.c72 uint32_t a8; member
166 arch_blk.r.a8 = frame->blks[regs_blk_remaining].r0; in arch_coredump_info_dump()
Dxtensa-asm2-util.S69 s32i a8, a1, 0
116 l32i a8, a2, 0
Dxtensa-asm2.c71 frame->a8 = (uintptr_t)arg2; /* a8 */ in xtensa_init_stack()
/Zephyr-Core-3.5.0/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdeh0213b72.overlay28 sdv = [41 a8 32];
51 sdv = [41 a8 32];
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S411 2: extui a8, a2, 28, 4 /* get next attribute nibble (msb first) */
412 extui a5, a8, 0, 2 /* lower two bit indicate whether cached */
416 addx4 a5, a8, a3 /* index into _xtos_mpu_attribs table */
417 addi a8, a8, -5 /* make valid attrib indices negative */
418 movgez a5, a3, a8 /* if not valid attrib, use Illegal */
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-context.h172 uintptr_t a8; member
193 uintptr_t a8; member
/Zephyr-Core-3.5.0/boards/arm/reel_board/
Dreel_board_v2.dts54 sdv = [41 a8 32];
98 sdv = [41 a8 32];
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/
Dpower_down_cavs.S41 #define temp_reg2 a8
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/
Dpower_down.S36 #define temp_reg2 a8
/Zephyr-Core-3.5.0/include/zephyr/
Ddevicetree.h4274 #define DT_CAT8(a1, a2, a3, a4, a5, a6, a7, a8) \ argument
4275 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7 ## a8