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/Zephyr-Core-3.5.0/arch/xtensa/core/
Ddebug_helpers_asm.S27 l32i a6, a5, 0
29 l32i a7, a6, ___xtensa_irq_bsa_t_pc_OFFSET
33 l32i a7, a6, ___xtensa_irq_bsa_t_a0_OFFSET
37 addi a6, a6, ___xtensa_irq_bsa_t_SIZEOF
39 s32i a6, a3, 0
Dcrt1.S42 # define ARG5 a6 /* 5th outgoing call argument */
46 # define ARG1 a6 /* 1st outgoing call argument */
167 movi a6, _bss_table_start
169 bgeu a6, a7, .L3zte
171 .L0zte: l32i a8, a6, 0 /* get start address, assumed multiple of 4 */
172 l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
173 addi a6, a6, 8 /* next entry */
191 bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
Dwindow_vectors.S141 s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
170 l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
199 s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
232 l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
Dcoredump.c70 uint32_t a6; member
160 arch_blk.r.a6 = frame->blks[regs_blk_remaining].r2; in arch_coredump_info_dump()
Dxtensa-asm2-util.S64 s32i a6, a1, 8
111 l32i a6, a2, 8
Dxtensa-asm2.c64 frame->a6 = (uintptr_t)entry; /* a6 */ in xtensa_init_stack()
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h21 unsigned long a6; member
43 unsigned long a6, unsigned long a7,
56 unsigned long a6, unsigned long a7,
/Zephyr-Core-3.5.0/arch/riscv/core/
Dcoredump.c26 uint32_t a6; member
78 arch_blk.r.a6 = esf->a6; in arch_coredump_info_dump()
Dfatal.c46 LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); in z_riscv_fatal_error()
Disr.S39 RV_I( op a6, __z_arch_esf_t_a6_OFFSET(sp) );\
434 mv a6, sp
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-context.h179 uintptr_t a6; member
200 uintptr_t a6; member
216 uintptr_t a6; member
Dxtensa-asm2-s.h350 mov a6, a3 /* place "new sp" in the next frame's A2 */
362 mov a2, a6 /* copy return value */
375 mov a2, a6 /* copy return value */
498 beq a6, a1, _restore_\@
508 mov a1, a6
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S402 movi a6, 8
424 addi a6, a6, -1
425 add a5, a5, a6 /* add the index */
427 bnez a6, 2b /* loop until done */
488 uploop: l32i a6, a5, 0
490 s32i a6, a3, 0
/Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
291 __ASSERT(a6, "a6 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
Dsip_svc_proto.h141 unsigned long a6; member
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
102 #define DEFINE_TEST_VARIANT6(name, variant, a1, a2, a3, a4, a5, a6) \ argument
105 test_##name(a1, a2, a3, a4, a5, a6); \
108 #define DEFINE_TEST_VARIANT7(name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
111 test_##name(a1, a2, a3, a4, a5, a6, a7); \
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dexp.h71 unsigned long a6; /* function argument */ member
/Zephyr-Core-3.5.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c119 unsigned long *a4, unsigned long *a5, unsigned long *a6, in intel_sip_smc_plat_async_res_req() argument
201 LOG_DBG("\tres->a6 %08lx", res->a6); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.5.0/arch/arm64/core/offsets/
Doffsets.c76 GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a6, a6_a7);
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/
Dpower_down_cavs.S39 #define temp_reg0 a6
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/
Dpower_down.S34 #define temp_reg0 a6
/Zephyr-Core-3.5.0/include/zephyr/
Ddevicetree.h4269 #define DT_CAT6(a1, a2, a3, a4, a5, a6) a1 ## a2 ## a3 ## a4 ## a5 ## a6 argument
4271 #define DT_CAT7(a1, a2, a3, a4, a5, a6, a7) \ argument
4272 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7
4274 #define DT_CAT8(a1, a2, a3, a4, a5, a6, a7, a8) \ argument
4275 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7 ## a8
/Zephyr-Core-3.5.0/subsys/sip_svc/
Dsip_svc_agilex_mailbox_shell.c142 request.a6 = 0; in cmd_close()
310 request.a6 = 0; in cmd_send()
Dsip_svc_subsys.c516 request.a5, request.a6, request.a7, &res); in sip_svc_request_handler()
561 unsigned long a6 = 0; in sip_svc_async_response_handler() local
576 if (sip_svc_plat_async_res_req(ctrl->dev, &a0, &a1, &a2, &a3, &a4, &a5, &a6, &a7, in sip_svc_async_response_handler()
586 sip_supervisory_call(ctrl->dev, a0, a1, a2, a3, a4, a5, a6, a7, &res); in sip_svc_async_response_handler()
/Zephyr-Core-3.5.0/arch/riscv/core/offsets/
Doffsets.c106 GEN_OFFSET_SYM(z_arch_esf_t, a6);

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