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/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S105 movi a2, XDM_MISC_PWRSTAT
111 rer a7, a2
202 rsr a2, ICOUNTLEVEL
206 bltui a2, 12, 1f
272 movi a2, _ResetSync /* address of sync variable */
276 beqz a2, .Ldonesync /* skip if no sync variable */
278 s32i a0, a2, 0 /* clear sync variable */
285 movi a2, XER_MPSCORE
286 wer a0, a2
296 movi a2, _memmap_vecbase_reset
[all …]
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dxtensa-asm2-util.S45 rsr a2, WINDOWSTART
46 slli a3, a2, (XCHAL_NUM_AREGS / 4)
47 or a2, a2, a3
50 srl a2, a2
60 bbsi a2, 1, _high_gpr_spill_done
67 bbsi a2, 2, _high_gpr_spill_done
74 bbsi a2, 3, _high_gpr_spill_done
103 l32i a2, a1, 0
105 mov a3, a2
107 beq a1, a2, _high_restore_done
[all …]
Dwindow_vectors.S58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
102 rsr a2, PS
103 extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
107 xor a2, a2, a3 /* flip changed bits in old window base */
108 wsr a2, PS /* update PS.OWB to new window base */
137 s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
164 l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
195 s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
226 l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */
Ddebug_helpers_asm.S31 s32i a7, a2, 0
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-s.h353 mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */
362 mov a2, a6 /* copy return value */
371 mov a1, a2
372 rsr.ZSR_EPS a2
373 wsr.PS a2
375 mov a2, a6 /* copy return value */
404 s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
409 l32i a2, a1, 0
410 l32i a2, a2, ___xtensa_irq_bsa_t_scratch_OFFSET
550 wsr.ZSR_EXTRA0 a2
[all …]
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dsyscall.h46 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
67 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
85 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
102 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h36 #define DEFINE_TEST_VARIANT2(suite, name, variant, a1, a2) \ argument
39 test_##name(a1, a2); \
42 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
45 test_##name(a1, a2, a3); \
48 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
51 test_##name(a1, a2, a3, a4); \
54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
[all …]
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h17 unsigned long a2; member
41 unsigned long a2, unsigned long a3,
54 unsigned long a2, unsigned long a3,
/Zephyr-Core-3.5.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
52 bt_addr_copy(&a2, BT_ADDR_INIT(0x22, 0x23, 0x24, 0x25, 0x26, 0x27)); in helper_prpa_add()
62 prpa_cache_add(&a2); in helper_prpa_add()
63 pos = prpa_cache_find(&a2); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
95 bt_addr_copy(&a2, BT_ADDR_INIT(0x22, 0x23, 0x24, 0x25, 0x26, 0x27)); in helper_trpa_add()
105 trpa_cache_add(&a2, 1); in helper_trpa_add()
106 pos = trpa_cache_find(&a2, 1); in helper_trpa_add()
/Zephyr-Core-3.5.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c97 if ((void *)request->a2 != NULL) { in intel_sip_smc_plat_update_trans_id()
98 data = (uint32_t *)request->a2; in intel_sip_smc_plat_update_trans_id()
112 if (request->a2) { in intel_sip_smc_plat_free_async_memory()
113 k_free((void *)request->a2); in intel_sip_smc_plat_free_async_memory()
118 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
127 *a2 = (unsigned long)buf; in intel_sip_smc_plat_async_res_req()
197 LOG_DBG("\tres->a2 %08lx", res->a2); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.5.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c25 register int a2 __asm__ ("a2") = SYS_write; in char_out()
31 : "=a"(a2), "=a"(a3) in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.5.0/subsys/bluetooth/crypto/
Dbt_crypto.c79 const bt_addr_le_t *a2, uint8_t *mackey, uint8_t *ltk) in bt_crypto_f5() argument
112 m[44] = a2->type; in bt_crypto_f5()
113 sys_memcpy_swap(m + 45, a2->a.val, 6); in bt_crypto_f5()
140 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2, in bt_crypto_f6() argument
153 LOG_DBG("a2 %s", bt_hex(a2, 7)); in bt_crypto_f6()
164 m[58] = a2->type; in bt_crypto_f6()
165 memcpy(m + 59, a2->a.val, 6); in bt_crypto_f6()
166 sys_memcpy_swap(m + 59, a2->a.val, 6); in bt_crypto_f6()
Dbt_crypto.h61 const bt_addr_le_t *a2, uint8_t *mackey, uint8_t *ltk);
81 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2,
/Zephyr-Core-3.5.0/drivers/console/
Dxtensa_sim_console.c20 register int a2 __asm__ ("a2") = SYS_write; in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
Dwinstream_console.c27 register int a2 __asm__("a2") = 4; /* SYS_write */ in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-Core-3.5.0/tests/bluetooth/bt_crypto/src/
Dtest_bt_crypto.c79 bt_addr_le_t a2 = {.type = 0x00, .a.val = {0xc1, 0xcf, 0x2d, 0x70, 0x13, 0xa7}}; in ZTEST() local
87 bt_crypto_f5(w, n1, n2, &a1, &a2, mackey, ltk); in ZTEST()
104 bt_addr_le_t a2 = {.type = 0x00, .a.val = {0xc1, 0xcf, 0x2d, 0x70, 0x13, 0xa7}}; in ZTEST() local
110 bt_crypto_f6(w, n1, n2, r, io_cap, &a1, &a2, res); in ZTEST()
/Zephyr-Core-3.5.0/arch/riscv/core/
Dcoredump.c21 uint32_t a2; member
69 arch_blk.r.a2 = esf->a2; in arch_coredump_info_dump()
Duserspace.S29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)
Dthread.c40 stack_init->a2 = (unsigned long)p2; in arch_new_thread()
180 register void *a2 __asm__("a2") = p2; in arch_user_mode_enter()
186 : "r" (a0), "r" (a1), "r" (a2), "r" (a3), "r" (top_of_user_stack) in arch_user_mode_enter()
/Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/
Dsip_svc_proto.h137 unsigned long a2; member
181 unsigned long a2; member
Dsip_svc_driver.h72 unsigned long *a1, unsigned long *a2, unsigned long *a3,
271 unsigned long *a1, unsigned long *a2, unsigned long *a3,
275 unsigned long *a1, unsigned long *a2, in z_impl_sip_svc_plat_async_res_req() argument
287 __ASSERT(a2, "a2 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
/Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/
DREADME.txt61 E: r0/a1: 0x20000000 r1/a2: 0x00000000 r2/a3: 0x20001e40
75 E: r0/a1: 0x00000003 r1/a2: 0x200020b8 r2/a3: 0x00000003
84 E: r0/a1: 0x00000004 r1/a2: 0x200020b8 r2/a3: 0x00000004
96 E: r0/a1: 0x00000004 r1/a2: 0x000000cf r2/a3: 0x00000000
108 E: r0/a1: 0x00000004 r1/a2: 0x00000017 r2/a3: 0x00000000
119 E: r0/a1: 0xdde8d9e7 r1/a2: 0x5510538d r2/a3: 0x00000d74
132 E: r0/a1: 0x00000000 r1/a2: 0x00000001 r2/a3: 0x00000002
/Zephyr-Core-3.5.0/include/zephyr/
Ddevicetree.h4261 #define DT_CAT(a1, a2) a1 ## a2 argument
4263 #define DT_CAT3(a1, a2, a3) a1 ## a2 ## a3 argument
4265 #define DT_CAT4(a1, a2, a3, a4) a1 ## a2 ## a3 ## a4 argument
4267 #define DT_CAT5(a1, a2, a3, a4, a5) a1 ## a2 ## a3 ## a4 ## a5 argument
4269 #define DT_CAT6(a1, a2, a3, a4, a5, a6) a1 ## a2 ## a3 ## a4 ## a5 ## a6 argument
4271 #define DT_CAT7(a1, a2, a3, a4, a5, a6, a7) \ argument
4272 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7
4274 #define DT_CAT8(a1, a2, a3, a4, a5, a6, a7, a8) \ argument
4275 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7 ## a8
/Zephyr-Core-3.5.0/include/zephyr/arch/mips/
Dexp.h37 unsigned long a2; /* function argument */ member
/Zephyr-Core-3.5.0/arch/mips/include/mips/
Dregdef.h28 #define a2 $6 macro

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