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Searched refs:XUARTPS_SR_OFFSET (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/serial/
Duart_xlnx_ps.c57 #define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ macro
346 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_in()
377 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_out()
383 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_out()
850 while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) { in uart_xlnx_ps_fifo_fill()
872 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_fifo_read()
879 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_fifo_read()
923 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_irq_tx_ready()
942 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_irq_tx_complete()