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Searched refs:XUARTPS_MR_OFFSET (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/serial/
Duart_xlnx_ps.c47 #define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ macro
304 reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
309 sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
609 mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_configure()
634 sys_write32(mode_reg, reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_configure()
817 uint32_t mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_config_get()