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Searched refs:XUARTPS_CR_OFFSET (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/serial/
Duart_xlnx_ps.c46 #define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ macro
182 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
187 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
206 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
211 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()