1 /* 2 * Copyright (c) 2018 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8 #ifndef _ARC_IOT_SYSCONF_H_ 9 #define _ARC_IOT_SYSCONF_H_ 10 11 #include <stdint.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 typedef struct sysconf_reg { 18 volatile uint32_t reserved1; /* 0x0 */ 19 volatile uint32_t AHBCLKDIV; /* AHB clock divisor */ 20 volatile uint32_t APBCLKDIV; /* APB clock divisor */ 21 volatile uint32_t APBCLKEN; /* APB module clock enable */ 22 volatile uint32_t CLKODIV; /* AHB clock output enable and divisor set */ 23 volatile uint32_t reserved2; /* 0x14 */ 24 volatile uint32_t RSTCON; /* reset contrl */ 25 volatile uint32_t RSTSTAT; /* reset status */ 26 volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */ 27 volatile uint32_t CLKSEL; /* main clock source select */ 28 volatile uint32_t PLLSTAT; /* PLL status register */ 29 volatile uint32_t PLLCON; /* PLL control register */ 30 volatile uint32_t reserved3; /* 0x30 */ 31 volatile uint32_t AHBCLKEN; /* AHB module clock enable */ 32 volatile uint32_t reserved4[2]; /* 0x38, 0x3c */ 33 volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */ 34 volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */ 35 volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */ 36 volatile uint32_t SDIO_REFCLK_DIV; /* SDIO reference clock divisor */ 37 volatile uint32_t GPIO4B_DBCLK_DIV; /* GPIO4B DBCLK divisor */ 38 volatile uint32_t IMAGE_CHK; /* Image pad status */ 39 volatile uint32_t PROT_RANGE; /* PROT range */ 40 volatile uint32_t SPI_MST_CLKDIV; /* SPI master clock divisor */ 41 volatile uint32_t DVFS_CLKDIV; /* DFSS main clock domain divider */ 42 volatile uint32_t DVFS_VDDSET; /* VDD setting */ 43 volatile uint32_t DVFS_VWTIME; /* VDD adjust waiting time */ 44 volatile uint32_t PMC_PUWTIME; /* power up waiting time */ 45 volatile uint32_t PMOD_MUX; /* PMOD IO mux */ 46 volatile uint32_t ARDUINO_MUX; /* arduino IO mux */ 47 volatile uint32_t USBPHY_PLL; /* USBPHY PLL */ 48 volatile uint32_t USBCFG; /* USB configuration */ 49 volatile uint32_t TIMER_PAUSE; /* PWM timer pause */ 50 volatile uint32_t GPIO8B_DBCLK_DIV; /* GPIO8B DBCLK divisor */ 51 volatile uint32_t RESET_PD_VECTOR; /* reset powerdown vector */ 52 volatile uint32_t UART3SCLK_DIV; /* UART3SCLK_DIV */ 53 } sysconf_reg_t; 54 55 /* CLKSEL_CONST is not described in spec. */ 56 #define CLKSEL_CONST (0x5A690000) 57 #define CLKSEL_EXT_16M (0 | CLKSEL_CONST) 58 #define CLKSEL_PLL (1 | CLKSEL_CONST) 59 #define CLKSEL_EXT_32K (2 | CLKSEL_CONST) 60 61 #define PLLCON_BIT_OFFSET_N 0 62 #define PLLCON_BIT_OFFSET_M 4 63 #define PLLCON_BIT_OFFSET_OD 20 64 #define PLLCON_BIT_OFFSET_BP 24 65 #define PLLCON_BIT_OFFSET_PLLRST 26 66 67 68 #define PLLSTAT_BIT_OFFSET_PLLSTB 2 69 #define PLLSTAT_BIT_OFFSET_PLLRDY 3 70 71 72 #define AHBCLKEN_BIT_I2S 0 73 #define AHBCLKEN_BIT_USB 1 74 #define AHBCLKEN_BIT_FLASH 2 75 #define AHBCLKEN_BIT_FMC 3 76 #define AHBCLKEN_BIT_DVFS 4 77 #define AHBCLKEN_BIT_PMC 5 78 #define AHBCLKEN_BIT_BOOT_SPI 6 79 #define AHBCLKEN_BIT_SDIO 7 80 81 #define APBCLKEN_BIT_ADC 0 82 #define APBCLKEN_BIT_I2S_TX 1 83 #define APBCLKEN_BIT_I2S_RX 2 84 #define APBCLKEN_BIT_RTC 3 85 #define APBCLKEN_BIT_PWM 4 86 #define APBCLKEN_BIT_I3C 5 87 88 89 #define SPI_MASTER_0 0 90 #define SPI_MASTER_1 1 91 #define SPI_MASTER_2 2 92 93 #define GPIO8B_BANK0 0 94 #define GPIO8B_BANK1 1 95 #define GPIO8B_BANK2 2 96 #define GPIO8B_BANK3 3 97 98 #define GPIO4B_BANK0 0 99 #define GPIO4B_BANK1 1 100 #define GPIO4B_BANK2 2 101 102 /* reset caused by power on */ 103 #define SYS_RST_SOFTWARE_ON 0x2 104 105 106 #define DVFS_PERF_LEVEL0 0 107 #define DVFS_PERF_LEVEL1 1 108 #define DVFS_PERF_LEVEL2 2 109 #define DVFS_PERF_LEVEL3 3 110 111 /* pmode mux definition */ 112 #define PMOD_MUX_PMA (0x1) 113 #define PMOD_MUX_PMB (0x2) 114 #define PMOD_MUX_PMC (0x4) 115 116 /* arduino mux definition */ 117 #define ARDUINO_MUX_UART (0x1) 118 #define ARDUINO_MUX_SPI (0x2) 119 #define ARDUINO_MUX_PWM0 (0x4) 120 #define ARDUINO_MUX_PWM1 (0x8) 121 #define ARDUINO_MUX_PWM2 (0x10) 122 #define ARDUINO_MUX_PWM3 (0x20) 123 #define ARDUINO_MUX_PWM4 (0x40) 124 #define ARDUINO_MUX_PWM5 (0x80) 125 #define ARDUINO_MUX_I2C (0x100) 126 #define ARDUINO_MUX_ADC0 (0x400) 127 #define ARDUINO_MUX_ADC1 (0x800) 128 #define ARDUINO_MUX_ADC2 (0x1000) 129 #define ARDUINO_MUX_ADC3 (0x2000) 130 #define ARDUINO_MUX_ADC4 (0x4000) 131 #define ARDUINO_MUX_ADC5 (0x8000) 132 133 #define PWM_TIMER0 0 134 #define PWM_TIMER1 1 135 #define PWM_TIMER2 2 136 #define PWM_TIMER3 3 137 #define PWM_TIMER4 4 138 #define PWM_TIMER5 5 139 140 141 extern void arc_iot_pll_conf_reg(uint32_t val); 142 extern int32_t arc_iot_pll_fout_config(uint32_t freq); 143 extern void arc_iot_ahb_clk_divisor(uint8_t div); 144 extern void arc_iot_ahb_clk_enable(uint8_t dev); 145 extern void arc_iot_ahb_clk_disable(uint8_t dev); 146 extern void arc_iot_sdio_clk_divisor(uint8_t div); 147 extern void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div); 148 extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div); 149 extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div); 150 extern void arc_iot_i2s_tx_clk_div(uint8_t div); 151 extern void arc_iot_i2s_rx_clk_div(uint8_t div); 152 extern void arc_iot_i2s_rx_clk_sel(uint8_t sel); 153 extern void arc_iot_syscon_reset(void); 154 extern uint32_t arc_iot_is_poweron_rst(void); 155 extern void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div); 156 extern void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val); 157 extern void arc_iot_dvfs_vwtime_config(uint8_t time); 158 extern void arc_iot_pmc_pwwtime_config(uint8_t time); 159 extern void arc_iot_uart3_clk_divisor(uint8_t div); 160 extern void arc_iot_reset_powerdown_vector(uint32_t addr); 161 extern void arc_iot_eflash_clk_div(uint8_t div); 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* _ARC_IOT_SYSCONF_H_ */ 168
