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/Zephyr-Core-3.5.0/tests/boards/intel_adsp/hda/src/
Dtests.h19 #define STREAM_SET_BASE(stream_set) CONCAT3(HDA_, stream_set, _BASE) macro
25 intel_adsp_hda_dbg(STREAM_SET_NAME(stream_set), STREAM_SET_BASE(stream_set), \