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Searched refs:STM32_PLL2_R_ENABLED (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_stm32_ll_h5.c134 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || in enabled_clock()
526 if (IS_ENABLED(STM32_PLL2_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c138 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || in enabled_clock()
591 if (IS_ENABLED(STM32_PLL2_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c348 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || in enabled_clock()
763 if (IS_ENABLED(STM32_PLL2_R_ENABLED)) { in set_up_plls()
/Zephyr-Core-3.5.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h175 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r) macro