1 /* ssd16xx_regs.h - Registers definition for SSD16XX compatible controller */
2 
3 /*
4  * Copyright (c) 2018 PHYTEC Messtechnik GmbH
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 
9 #ifndef __SSD16XX_REGS_H__
10 #define __SSD16XX_REGS_H__
11 
12 #define SSD16XX_CMD_GDO_CTRL			0x01
13 #define SSD16XX_CMD_GDV_CTRL			0x03
14 #define SSD16XX_CMD_SDV_CTRL			0x04
15 #define SSD16XX_CMD_SOFTSTART			0x0c
16 #define SSD16XX_CMD_GSCAN_START			0x0f
17 #define SSD16XX_CMD_SLEEP_MODE			0x10
18 #define SSD16XX_CMD_ENTRY_MODE			0x11
19 #define SSD16XX_CMD_SW_RESET			0x12
20 #define SSD16XX_CMD_TSENSOR_SELECTION		0x18
21 #define SSD16XX_CMD_TSENS_CTRL			0x1a
22 #define SSD16XX_CMD_READ_TSENS_CTRL		0x1b
23 #define SSD16XX_CMD_MASTER_ACTIVATION		0x20
24 #define SSD16XX_CMD_UPDATE_CTRL1		0x21
25 #define SSD16XX_CMD_UPDATE_CTRL2		0x22
26 #define SSD16XX_CMD_WRITE_RAM			0x24
27 #define SSD16XX_CMD_WRITE_RED_RAM		0x26
28 #define SSD16XX_CMD_READ_RAM			0x27
29 #define SSD16XX_CMD_VCOM_SENSE			0x28
30 #define SSD16XX_CMD_VCOM_SENSE_DURATON		0x29
31 #define SSD16XX_CMD_PRGM_VCOM_OTP		0x2a
32 #define SSD16XX_CMD_VCOM_VOLTAGE		0x2c
33 #define SSD16XX_CMD_READ_OTP_REG		0x2d
34 #define SSD16XX_CMD_READ_USER_ID		0x2e
35 #define SSD16XX_CMD_READ_STATUS			0x2f
36 #define SSD16XX_CMD_PRGM_WS_OTP			0x30
37 #define SSD16XX_CMD_LOAD_WS_OTP			0x31
38 #define SSD16XX_CMD_UPDATE_LUT			0x32
39 #define SSD16XX_CMD_PRGM_OTP_SELECTION		0x36
40 #define SSD16XX_CMD_OTP_SELECTION_CTRL		0x37
41 #define SSD16XX_CMD_DUMMY_LINE			0x3a
42 #define SSD16XX_CMD_GATE_LINE_WIDTH		0x3b
43 #define SSD16XX_CMD_BWF_CTRL			0x3c
44 #define SSD16XX_CMD_RAM_READ_CTRL		0x41
45 #define SSD16XX_CMD_RAM_XPOS_CTRL		0x44
46 #define SSD16XX_CMD_RAM_YPOS_CTRL		0x45
47 #define SSD16XX_CMD_RAM_XPOS_CNTR		0x4e
48 #define SSD16XX_CMD_RAM_YPOS_CNTR		0x4f
49 
50 /* Data entry sequence modes */
51 #define SSD16XX_DATA_ENTRY_MASK			0x07
52 #define SSD16XX_DATA_ENTRY_XDYDX		0x00
53 #define SSD16XX_DATA_ENTRY_XIYDX		0x01
54 #define SSD16XX_DATA_ENTRY_XDYIX		0x02
55 #define SSD16XX_DATA_ENTRY_XIYIX		0x03
56 #define SSD16XX_DATA_ENTRY_XDYDY		0x04
57 #define SSD16XX_DATA_ENTRY_XIYDY		0x05
58 #define SSD16XX_DATA_ENTRY_XDYIY		0x06
59 #define SSD16XX_DATA_ENTRY_XIYIY		0x07
60 
61 /* Options for display update */
62 #define SSD16XX_CTRL1_INITIAL_UPDATE_LL		0x00
63 #define SSD16XX_CTRL1_INITIAL_UPDATE_LH		0x01
64 #define SSD16XX_CTRL1_INITIAL_UPDATE_HL		0x02
65 #define SSD16XX_CTRL1_INITIAL_UPDATE_HH		0x03
66 
67 /* Options for display update sequence */
68 #define SSD16XX_CTRL2_ENABLE_CLK		0x80
69 #define SSD16XX_CTRL2_ENABLE_ANALOG		0x40
70 #define SSD16XX_CTRL2_LOAD_TEMPERATURE		0x20
71 #define SSD16XX_CTRL2_LOAD_LUT			0x10
72 #define SSD16XX_CTRL2_DISABLE_ANALOG		0x02
73 #define SSD16XX_CTRL2_DISABLE_CLK		0x01
74 
75 #define SSD16XX_GEN1_CTRL2_TO_INITIAL		0x08
76 #define SSD16XX_GEN1_CTRL2_TO_PATTERN		0x04
77 
78 #define SSD16XX_GEN2_CTRL2_MODE2		0x08
79 #define SSD16XX_GEN2_CTRL2_DISPLAY		0x04
80 
81 #define SSD16XX_SLEEP_MODE_DSM			0x01
82 #define SSD16XX_SLEEP_MODE_PON			0x00
83 
84 #define SSD16XX_RAM_READ_CTRL_BLACK		0
85 #define SSD16XX_RAM_READ_CTRL_RED		1
86 
87 /* time constants in ms */
88 #define SSD16XX_RESET_DELAY			1
89 #define SSD16XX_BUSY_DELAY			1
90 
91 #endif /* __SSD16XX_REGS_H__ */
92