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Searched refs:SRC (Results 1 – 18 of 18) sorted by relevance

/Zephyr-Core-3.5.0/modules/cmsis-nn/
DCMakeLists.txt18 file(GLOB SRC "${CMSIS_NN_DIR}/Source/ActivationFunctions/*_s8*.c")
20 zephyr_library_sources(${SRC} ${SRC_S16}
26 file(GLOB SRC "${CMSIS_NN_DIR}/Source/BasicMathFunctions/*_*.c")
27 zephyr_library_sources(${SRC})
31 file(GLOB SRC "${CMSIS_NN_DIR}/Source/ConcatenationFunctions/*_*.c")
32 zephyr_library_sources(${SRC})
36 file(GLOB SRC "${CMSIS_NN_DIR}/Source/ConvolutionFunctions/*_s8*.c")
38 zephyr_library_sources(${SRC} ${SRC_S16})
42 file(GLOB SRC "${CMSIS_NN_DIR}/Source/FullyConnectedFunctions/*_s8.c")
44 zephyr_library_sources(${SRC} ${SRC_S16})
[all …]
/Zephyr-Core-3.5.0/samples/subsys/usb_c/source/
DREADME.rst48 UnattachedWait.SRC
49 Unattached.SRC
50 AttachWait.SRC
51 Attached.SRC
/Zephyr-Core-3.5.0/scripts/build/
Dgen_app_partitions.py46 SRC = 'sources' variable
133 partitions[partition_name][SRC] = filename
198 partitions[partition_name][SRC] = args.elf
303 partsorted[key][SRC]))
317 partsorted[key][SRC]))
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Ddevice_power.c77 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_en()
88 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_dis()
100 regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT; in soc_deep_sleep_wake_en()
105 regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT; in soc_deep_sleep_wake_en()
118 regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT; in soc_deep_sleep_wake_dis()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
Dsoc_saml2x.c42 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val; in gclk_reset()
215 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val; in gclk_main_configure()
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Ddevice_power.c96 GIRQ22_REGS->SRC = 0xfffffffful; in soc_deep_sleep_non_wake_en()
105 GIRQ22_REGS->SRC = 0xfffffffful; in soc_deep_sleep_non_wake_dis()
Dsoc.c37 pg->SRC = 0xFFFFFFFFul; in soc_ecia_init()
/Zephyr-Core-3.5.0/drivers/hwinfo/
DKconfig90 bool "NXP SRC reset cause"
94 Enable NXP i.MX mcux SRC hwinfo driver.
97 bool "NXP SRC reset cause (multicore devices)"
101 Enable version 2 multicore NXP i.MX mcux SRC hwinfo driver.
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_mchp_xec.c242 girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS); in pll_wait_lock_periph()
246 if (girq23->SRC & BIT(XEC_CC_HTMR_0_GIRQ23_POS)) { in pll_wait_lock_periph()
410 girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS); in hib_timer_delay()
416 while ((girq23->SRC & BIT(XEC_CC_HTMR_0_GIRQ23_POS)) == 0) { in hib_timer_delay()
424 girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS); in hib_timer_delay()
501 girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS); in check_32k_crystal()
520 while ((girq23->SRC & BIT(XEC_CC_HTMR_0_GIRQ23_POS)) == 0) { in check_32k_crystal()
540 girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS); in check_32k_crystal()
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_espi_vw.h288 volatile uint32_t SRC; member
327 volatile uint32_t SRC; member
Dmec172x_ecia.h1131 volatile uint32_t SRC; member
1199 ecia->GIRQ[girq - 8u].SRC = BIT(pin); in mchp_soc_ecia_girq_src_clr()
1211 ecia->GIRQ[girq - 8u].SRC = bitmap; in mchp_soc_ecia_girq_src_clr_bitmap()
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_mchp_ecia_xec.c104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
140 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = bitmap; in mchp_xec_ecia_girq_src_clr_bitmap()
494 girq->SRC = BIT(bitpos); in xec_girq_isr()
/Zephyr-Core-3.5.0/subsys/bluetooth/mesh/
Dnet.c58 #define SRC(pdu) (sys_get_be16(&(pdu)[5])) macro
152 if (msg_cache[--i].src == SRC(pdu->data) && in msg_cache_match()
159 if (msg_cache[--i].src == SRC(pdu->data) && in msg_cache_match()
411 .addr = SRC(buf->data), in bt_mesh_net_local()
644 rx->ctx.addr = SRC(out->data); in net_decrypt()
773 rx->ctx.addr = SRC(buf->data); in bt_mesh_net_header_parse()
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/
Dsoc_rt11xx.c710 SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK; in second_core_boot()
711 SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; in second_core_boot()
/Zephyr-Core-3.5.0/drivers/timer/
Dmchp_xec_rtos_timer.c118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
/Zephyr-Core-3.5.0/drivers/espi/
Despi_mchp_xec.c450 uint8_t *p8 = (uint8_t *)&reg->SRC; in espi_xec_send_vwire()
457 uint8_t *p8 = (uint8_t *)&reg->SRC; in espi_xec_send_vwire()
488 *level = ((reg->SRC >> (src_id << 3)) & 0x01ul); in espi_xec_receive_vwire()
493 *level = ((reg->SRC >> (src_id << 3)) & 0x01ul); in espi_xec_receive_vwire()
/Zephyr-Core-3.5.0/modules/
DKconfig.mcux217 Set if the system reset controller (SRC) module is present in the
223 Set if version 2 of the system reset controller (SRC) module is
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.5.rst158 * Removed ``CONFIG_BT_PACS_{SNK,SRC}_CONTEXT``