1 /* 2 * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ 8 #define ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ 9 10 #include <zephyr/drivers/pinctrl.h> 11 #include <hal/spi_hal.h> 12 #ifdef SOC_GDMA_SUPPORTED 13 #include <hal/gdma_hal.h> 14 #endif 15 16 #define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10) 17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */ 18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */ 19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */ 20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */ 21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */ 22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */ 23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */ 24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */ 25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */ 26 27 struct spi_esp32_config { 28 spi_dev_t *spi; 29 const struct device *clock_dev; 30 int duty_cycle; 31 int input_delay_ns; 32 int irq_source; 33 const struct pinctrl_dev_config *pcfg; 34 clock_control_subsys_t clock_subsys; 35 bool use_iomux; 36 bool dma_enabled; 37 int dma_clk_src; 38 int dma_host; 39 int cs_setup; 40 int cs_hold; 41 bool line_idle_low; 42 }; 43 44 struct spi_esp32_data { 45 struct spi_context ctx; 46 spi_hal_context_t hal; 47 spi_hal_config_t hal_config; 48 #ifdef SOC_GDMA_SUPPORTED 49 gdma_hal_context_t hal_gdma; 50 #endif 51 spi_hal_timing_conf_t timing_config; 52 spi_hal_dev_config_t dev_config; 53 spi_hal_trans_config_t trans_config; 54 uint8_t dfs; 55 int irq_line; 56 lldesc_t dma_desc_tx; 57 lldesc_t dma_desc_rx; 58 }; 59 60 #endif /* ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ */ 61
