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Searched refs:SHLU32 (Results 1 – 13 of 13) sorted by relevance

/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_gpio.h38 #define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS)
39 #define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS)
40 #define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
41 #define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
47 #define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1, MCHP_GPIO_CTRL_IDET_POS)
48 #define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4, MCHP_GPIO_CTRL_IDET_POS)
49 #define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xd, MCHP_GPIO_CTRL_IDET_POS)
50 #define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xe, MCHP_GPIO_CTRL_IDET_POS)
51 #define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
52 #define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
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Dmec172x_qspi.h159 #define MCHP_QMSPI_M_SIG_MODE1 SHLU32(6u, MCHP_QMSPI_M_SIG_POS)
160 #define MCHP_QMSPI_M_SIG_MODE2 SHLU32(1u, MCHP_QMSPI_M_SIG_POS)
161 #define MCHP_QMSPI_M_SIG_MODE3 SHLU32(7u, MCHP_QMSPI_M_SIG_POS)
164 #define MCHP_QMSPI_M_CS_MASK SHLU32(3u, 12)
165 #define MCHP_QMSPI_M_CS0 SHLU32(0u, 12)
166 #define MCHP_QMSPI_M_CS1 SHLU32(1u, 12)
180 #define MCHP_QMSPI_C_TX_MASK SHLU32(3u, MCHP_QMSPI_C_TX_POS)
182 #define MCHP_QMSPI_C_TX_DATA SHLU32(1u, MCHP_QMSPI_C_TX_POS)
183 #define MCHP_QMSPI_C_TX_ZEROS SHLU32(2u, MCHP_QMSPI_C_TX_POS)
184 #define MCHP_QMSPI_C_TX_ONES SHLU32(3u, MCHP_QMSPI_C_TX_POS)
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Dmec172x_espi_iom.h44 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK SHLU32(0x03u, 4)
50 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_1, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
53 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_12, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
56 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_14, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
59 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_124, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
103 SHLU32(MCHP_ESPI_FC_CAP_SHARE_MASK0, MCHP_ESPI_FC_CAP_SHARE_POS)
107 SHLU32(1U, MCHP_ESPI_FC_CAP_SHARE_POS)
110 SHLU32(2U, MCHP_ESPI_FC_CAP_SHARE_POS)
113 SHLU32(3U, MCHP_ESPI_FC_CAP_SHARE_POS)
118 SHLU32(MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0, \
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Dmec172x_espi_vw.h41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
56 #define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xfu, ((n) * 8u))
57 #define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
122 #define ESPI_S2MW1_SRC_POS(n) SHLU32((n), 3)
124 SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n)))
173 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC0_IRQ_SEL_POS)
175 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC1_IRQ_SEL_POS)
177 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC2_IRQ_SEL_POS)
179 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC3_IRQ_SEL_POS)
Dmec172x_espi_saf.h226 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS)
230 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS)
277 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP0_STM1_POS)
280 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM2_POS)
283 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM3_POS)
286 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM4_POS)
289 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM5_POS)
292 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM6_POS)
295 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM7_POS)
305 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STM9_POS)
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Dmec172x_ecs.h39 SHLU32(MCHP_ECS_DCTRL_DBG_MODE_MASK0, MCHP_ECS_DCTRL_DBG_MODE_POS)
43 #define MCHP_ECS_DCTRL_MODE_SWD SHLU32(0x02u, 1u)
44 #define MCHP_ECS_DCTRL_MODE_SWD_SWV SHLU32(0x01u, 1u)
Dmec172x_defs.h80 #define SHLU32(v, n) ((uint32_t)(v) << (n)) macro
Dmec172x_i2c_smb.h203 #define MCHP_I2C_SMB_BB_IN_MASK SHLU32(0x03, 5)
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_tach.h40 #define MCHP_TACH_CTRL_NUM_EDGES_MASK SHLU32(0x03U, 11)
42 #define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11)
43 #define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11)
44 #define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11)
57 #define MCHP_TACH_CTRL_COUNTER_MASK SHLU32(0xffffU, 16)
Dmec_adc.h74 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8)
79 #define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u))
81 #define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u))
91 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1fffu, 16)
97 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(3u, 30)
119 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7)
120 #define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7)
Dmec_timers.h122 #define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4)
124 #define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1, 4)
125 #define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2, 4)
126 #define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3, 4)
127 #define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4, 4)
128 #define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5, 4)
129 #define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6, 4)
130 #define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7, 4)
Dmec_pwm.h51 SHLU32(0x0fu, MCHP_PWM_CFG_CLK_PRE_DIV_POS)
54 SHLU32((n) & MCHP_PWM_CFG_CLK_PRE_DIV_MASK0, \
Dmec_acpi_ec.h79 #define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK SHLU32(3, 2)