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Searched refs:SCTLR_M_BIT (Results 1 – 5 of 5) sorted by relevance

/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_a_r/
Dcpu.h52 #define SCTLR_M_BIT BIT(0) macro
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Dcpu.h50 #define SCTLR_M_BIT BIT(0) macro
/Zephyr-Core-3.5.0/arch/arm64/core/cortex_r/
Darm_mpu.c99 val |= SCTLR_M_BIT; in arm_core_mpu_enable()
116 val &= ~SCTLR_M_BIT; in arm_core_mpu_disable()
/Zephyr-Core-3.5.0/arch/arm64/core/
Dmmu.c841 write_sctlr_el1(val | SCTLR_M_BIT | SCTLR_C_BIT); in enable_mmu_el1()
873 __ASSERT((read_sctlr_el1() & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); in z_arm64_mm_init()
/Zephyr-Core-3.5.0/tests/kernel/mem_protect/userspace/src/
Dmain.c219 : "r" (val & ~(SCTLR_M_BIT | SCTLR_C_BIT)) in ZTEST_USER()