1 /* 2 * Copyright (c) 2020 TDK Invensense 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ICM42605_ICM42605_REG_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ICM42605_ICM42605_REG_H_ 9 10 /* BANK 0 */ 11 #define REG_DEVICE_CONFIG 0x11 12 #define REG_DRIVE_CONFIG 0x13 13 #define REG_INT_CONFIG 0x14 14 #define REG_FIFO_CONFIG 0x16 15 #define REG_TEMP_DATA1 0x1D 16 #define REG_TEMP_DATA0 0x1E 17 #define REG_ACCEL_DATA_X1 0x1F 18 #define REG_ACCEL_DATA_X0 0x20 19 #define REG_ACCEL_DATA_Y1 0x21 20 #define REG_ACCEL_DATA_Y0 0x22 21 #define REG_ACCEL_DATA_Z1 0x23 22 #define REG_ACCEL_DATA_Z0 0x24 23 #define REG_GYRO_DATA_X1 0x25 24 #define REG_GYRO_DATA_X0 0x26 25 #define REG_GYRO_DATA_Y1 0x27 26 #define REG_GYRO_DATA_Y0 0x28 27 #define REG_GYRO_DATA_Z1 0x29 28 #define REG_GYRO_DATA_Z0 0x2A 29 #define REG_TMST_FSYNCH 0x2B 30 #define REG_TMST_FSYNCL 0x2C 31 #define REG_INT_STATUS 0x2D 32 #define REG_FIFO_COUNTH 0x2E 33 #define REG_FIFO_COUNTL 0x2F 34 #define REG_FIFO_DATA 0x30 35 #define REG_APEX_DATA0 0x31 36 #define REG_APEX_DATA1 0x32 37 #define REG_APEX_DATA2 0x33 38 #define REG_APEX_DATA3 0x34 39 #define REG_APEX_DATA4 0x35 40 #define REG_APEX_DATA5 0x36 41 #define REG_INT_STATUS2 0x37 42 #define REG_INT_STATUS3 0x38 43 #define REG_SIGNAL_PATH_RESET 0x4B 44 #define REG_INTF_CONFIG0 0x4C 45 #define REG_INTF_CONFIG1 0x4D 46 #define REG_PWR_MGMT0 0x4E 47 #define REG_GYRO_CONFIG0 0x4F 48 #define REG_ACCEL_CONFIG0 0x50 49 #define REG_GYRO_CONFIG1 0x51 50 #define REG_GYRO_ACCEL_CONFIG0 0x52 51 #define REG_ACCEL_CONFIG1 0x53 52 #define REG_TMST_CONFIG 0x54 53 #define REG_APEX_CONFIG0 0x56 54 #define REG_SMD_CONFIG 0x57 55 #define REG_FIFO_CONFIG1 0x5F 56 #define REG_FIFO_CONFIG2 0x60 57 #define REG_FIFO_CONFIG4 0x61 58 #define REG_FIFO_FSYNC_CONFIG 0x62 59 #define REG_INT_CONFIG0 0x63 60 #define REG_INT_CONFIG1 0x64 61 #define REG_INT_SOURCE0 0x65 62 #define REG_INT_SOURCE1 0x66 63 #define REG_INT_SOURCE3 0x68 64 #define REG_INT_SOURCE4 0x69 65 #define REG_FIFO_LOST_PKT0 0x6C 66 #define REG_FIFO_LOST_PKT1 0x6D 67 #define REG_SELF_TEST_CONFIG 0x70 68 #define REG_WHO_AM_I 0x75 69 #define REG_BANK_SEL 0x76 70 71 /* BANK 1 */ 72 #define REG_SENSOR_CONFIG0 0x03 73 #define REG_GYRO_CONFIG_STATIC2 0x0B 74 #define REG_GYRO_CONFIG_STATIC3 0x0C 75 #define REG_GYRO_CONFIG_STATIC4 0x0D 76 #define REG_GYRO_CONFIG_STATIC5 0x0E 77 #define REG_GYRO_CONFIG_STATIC6 0x0F 78 #define REG_GYRO_CONFIG_STATIC7 0x10 79 #define REG_GYRO_CONFIG_STATIC8 0x11 80 #define REG_GYRO_CONFIG_STATIC9 0x12 81 #define REG_GYRO_CONFIG_STATIC10 0x13 82 #define REG_XG_ST_DATA 0x5F 83 #define REG_YG_ST_DATA 0x60 84 #define REG_ZG_ST_DATA 0x61 85 #define REG_TMSTVAL0 0x62 86 #define REG_TMSTVAL1 0x63 87 #define REG_TMSTVAL2 0x64 88 #define REG_INTF_CONFIG4 0x7A 89 #define REG_INTF_CONFIG5 0x7B 90 #define REG_INTF_CONFIG6 0x7C 91 92 /* BANK 2 */ 93 #define REG_ACCEL_CONFIG_STATIC2 0x03 94 #define REG_ACCEL_CONFIG_STATIC3 0x04 95 #define REG_ACCEL_CONFIG_STATIC4 0x05 96 #define REG_XA_ST_DATA 0x3B 97 #define REG_YA_ST_DATA 0x3C 98 #define REG_ZA_ST_DATA 0x3D 99 100 /* BANK 4 */ 101 #define REG_GYRO_ON_OFF_CONFIG 0x0E 102 #define REG_APEX_CONFIG1 0x40 103 #define REG_APEX_CONFIG2 0x41 104 #define REG_APEX_CONFIG3 0x42 105 #define REG_APEX_CONFIG4 0x43 106 #define REG_APEX_CONFIG5 0x44 107 #define REG_APEX_CONFIG6 0x45 108 #define REG_APEX_CONFIG7 0x46 109 #define REG_APEX_CONFIG8 0x47 110 #define REG_APEX_CONFIG9 0x48 111 #define REG_ACCEL_WOM_X_THR 0x4A 112 #define REG_ACCEL_WOM_Y_THR 0x4B 113 #define REG_ACCEL_WOM_Z_THR 0x4C 114 #define REG_INT_SOURCE6 0x4D 115 #define REG_INT_SOURCE7 0x4E 116 #define REG_INT_SOURCE8 0x4F 117 #define REG_INT_SOURCE9 0x50 118 #define REG_INT_SOURCE10 0x51 119 #define REG_OFFSET_USER0 0x77 120 #define REG_OFFSET_USER1 0x78 121 #define REG_OFFSET_USER2 0x79 122 #define REG_OFFSET_USER3 0x7A 123 #define REG_OFFSET_USER4 0x7B 124 #define REG_OFFSET_USER5 0x7C 125 #define REG_OFFSET_USER6 0x7D 126 #define REG_OFFSET_USER7 0x7E 127 #define REG_OFFSET_USER8 0x7F 128 129 /* #define REG_#define REG_BANK_SEL */ 130 #define BIT_BANK_SEL_0 0x00 131 #define BIT_BANK_SEL_1 0x01 132 #define BIT_BANK_SEL_2 0x02 133 #define BIT_BANK_SEL_3 0x03 134 #define BIT_BANK_SEL_4 0x04 135 136 #define WHO_AM_I_ICM42605 0x42 137 138 /* Bank0 #define REG_DEVICE_CONFIG_REG */ 139 #define BIT_SOFT_RESET 0x01 140 141 /* Bank0 #define REG_GYRO_CONFIG0, REG_ACCEL_CONFIG0 */ 142 #define SHIFT_GYRO_FS_SEL 5 143 #define SHIFT_ACCEL_FS_SEL 5 144 #define SHIFT_ODR_CONF 0 145 146 /* Bank0 #define REG_GYRO_CONFIG1 */ 147 #define BIT_TEMP_FILT_BW_BYPASS 0x00 148 #define BIT_TEMP_FILT_BW_170 0x20 149 #define BIT_TEMP_FILT_BW_82 0x40 150 #define BIT_TEMP_FILT_BW_40 0x60 151 #define BIT_TEMP_FILT_BW_20 0x80 152 #define BIT_TEMP_FILT_BW_10 0x90 153 #define BIT_TEMP_FILT_BW_5 0xC0 154 #define BIT_GYR_AVG_FLT_RATE_8KHZ 0x10 155 #define BIT_GYR_AVG_FLT_RATE_1KHZ 0x00 156 #define BIT_GYR_UI_FILT_ORD_IND_1 0x00 157 #define BIT_GYR_UI_FILT_ORD_IND_2 0x04 158 #define BIT_GYR_UI_FILT_ORD_IND_3 0x08 159 #define BIT_GYR_DEC2_M2_ORD_1 0x00 160 #define BIT_GYR_DEC2_M2_ORD_2 0x01 161 #define BIT_GYR_DEC2_M2_ORD_3 0x02 162 163 /* Bank0 REG_ACCEL_CONFIG1 */ 164 #define BIT_ACC_UI_FILT_ODR_IND_1 0x00 165 #define BIT_ACC_UI_FILT_ODR_IND_2 0x08 166 #define BIT_ACC_UI_FILT_ODR_IND_3 0x10 167 #define BIT_ACC_DEC2_M2_ORD_1 0x00 168 #define BIT_ACC_DEC2_M2_ORD_2 0x02 169 #define BIT_ACC_DEC2_M2_ORD_3 0x04 170 #define BIT_ACC_AVG_FLT_RATE_8KHZ 0x01 171 #define BIT_ACC_AVG_FLT_RATE_1KHZ 0x00 172 173 /* Bank0 REG_INT_CONFIG_REG */ 174 #define SHIFT_INT1_POLARITY 0 175 #define SHIFT_INT1_DRIVE_CIRCUIT 1 176 #define SHIFT_INT1_MODE 2 177 178 /* Bank0 REG_PWR_MGMT_0 */ 179 #define BIT_TEMP_DIS 0x20 180 #define BIT_IDLE 0x10 181 #define BIT_GYRO_MODE_OFF 0x00 182 #define BIT_GYRO_MODE_STBY 0x04 183 #define BIT_GYRO_MODE_LPM 0x08 184 #define BIT_GYRO_MODE_LNM 0x0C 185 #define BIT_ACCEL_MODE_OFF 0x00 186 #define BIT_ACCEL_MODE_LPM 0x02 187 #define BIT_ACCEL_MODE_LNM 0x03 188 189 /* Bank0 REG_SIGNAL_PATH_RESET */ 190 #define BIT_TEMP_RST 0x01 191 #define BIT_FIFO_FLUSH 0x02 192 #define BIT_TMST_STROBE 0x04 193 #define BIT_ABORT_AND_RESET 0x08 194 #define BIT_S4S_RESTART 0x10 195 #define BIT_DMP_MEM_RESET_EN 0x20 196 #define BIT_DMP_INIT_EN 0x40 197 198 /* Bank0 REG_INTF_CONFIG0 */ 199 #define BIT_FIFO_COUNT_REC 0x40 200 #define BIT_COUNT_BIG_ENDIAN 0x20 201 #define BIT_SENS_DATA_BIG_ENDIAN 0x10 202 #define BIT_UI_SIFS_DISABLE_SPI 0x02 203 #define BIT_UI_SIFS_DISABLE_I2C 0x03 204 205 /* Bank0 REG_INTF_CONFIG1 */ 206 #define BIT_GYRO_AFSR_MODE_LFS 0x00 207 #define BIT_GYRO_AFSR_MODE_HFS 0x40 208 #define BIT_GYRO_AFSR_MODE_DYN 0xC0 209 #define BIT_ACCEL_AFSR_MODE_LFS 0x00 210 #define BIT_ACCEL_AFSR_MODE_HFS 0x10 211 #define BIT_ACCEL_AFSR_MODE_DYN 0x30 212 #define BIT_ACCEL_LP_CLK_SEL 0x08 213 #define BIT_RTC_MODE 0x04 214 #define BIT_CLK_SEL_RC 0x00 215 #define BIT_CLK_SEL_PLL 0x01 216 #define BIT_CLK_SEL_DIS 0x03 217 218 /* Bank0 REG_FIFO_CONFIG1 */ 219 #define BIT_FIFO_ACCEL_EN 0x01 220 #define BIT_FIFO_GYRO_EN 0x02 221 #define BIT_FIFO_TEMP_EN 0x04 222 #define BIT_FIFO_TMST_FSYNC_EN 0x08 223 #define BIT_FIFO_HIRES_EN 0x10 224 #define BIT_FIFO_WM_TH 0x20 225 #define BIT_FIFO_RESUME_PART_RD 0x40 226 227 /* Bank0 REG_INT_CONFIG1 */ 228 #define BIT_INT_ASY_RST_DISABLE 0x10 229 230 /* Bank0 REG_INT_SOURCE0 */ 231 #define BIT_INT_UI_AGC_RDY_INT1_EN 0x01 232 #define BIT_INT_FIFO_FULL_INT1_EN 0x02 233 #define BIT_INT_FIFO_THS_INT1_EN 0x04 234 #define BIT_INT_UI_DRDY_INT1_EN 0x08 235 #define BIT_INT_RESET_DONE_INT1_EN 0x10 236 #define BIT_INT_PLL_RDY_INT1_EN 0x20 237 #define BIT_INT_UI_FSYNC_INT1_EN 0x40 238 239 /* Bank0 REG_INT_SOURCE1 */ 240 #define BIT_INT_WOM_X_INT1_EN 0x01 241 #define BIT_INT_WOM_Y_INT1_EN 0x02 242 #define BIT_INT_WOM_Z_INT1_EN 0x04 243 #define BIT_INT_SMD_INT1_EN 0x08 244 #define BIT_INT_WOM_XYZ_INT1_EN \ 245 (BIT_INT_WOM_X_INT1_EN | BIT_INT_WOM_Y_INT1_EN | BIT_INT_WOM_Z_INT1_EN) 246 247 /* Bank0 REG_SENSOR_SELFTEST_REG1 */ 248 #define BIT_ACCEL_SELF_TEST_PASS 0x08 249 #define BIT_GYRO_SELF_TEST_PASS 0x04 250 #define BIT_ACCEL_SELF_TEST_DONE 0x02 251 #define BIT_GYRO_SELF_TEST_DONE 0x01 252 253 /* Bank0 REG_SELF_TEST_CONFIG */ 254 #define BIT_SELF_TEST_REGULATOR_EN 0x40 255 #define BIT_TEST_AZ_EN 0x20 256 #define BIT_TEST_AY_EN 0x10 257 #define BIT_TEST_AX_EN 0x08 258 #define BIT_TEST_GZ_EN 0x04 259 #define BIT_TEST_GY_EN 0x02 260 #define BIT_TEST_GX_EN 0x01 261 262 /* Bank0 REG_INT_STATUS */ 263 #define BIT_INT_STATUS_AGC_RDY 0x01 264 #define BIT_INT_STATUS_FIFO_FULL 0x02 265 #define BIT_INT_STATUS_FIFO_THS 0x04 266 #define BIT_INT_STATUS_DRDY 0x08 267 #define BIT_INT_STATUS_RESET_DONE 0x10 268 #define BIT_INT_STATUS_PLL_DRY 0x20 269 #define BIT_INT_STATUS_UI_FSYNC 0x40 270 271 /* Bank0 REG_INT_STATUS2 */ 272 #define BIT_INT_STATUS_WOM_X 0x01 273 #define BIT_INT_STATUS_WOM_Y 0x02 274 #define BIT_INT_STATUS_WOM_Z 0x04 275 #define BIT_INT_STATUS_SMD 0x08 276 #define BIT_INT_STATUS_WOM_XYZ \ 277 (BIT_INT_STATUS_WOM_X | BIT_INT_STATUS_WOM_Y | BIT_INT_STATUS_WOM_Z) 278 279 /* Bank0 REG_INT_STATUS3 */ 280 #define BIT_INT_STATUS_TAP_DET 0x01 281 #define BIT_INT_STATUS_SLEEP_DET 0x02 282 #define BIT_INT_STATUS_RAISE_DET 0x04 283 #define BIT_INT_STATUS_TILT_DET 0x08 284 #define BIT_INT_STATUS_STEP_CNT_OVFL 0x10 285 #define BIT_INT_STATUS_STEP_DET 0x20 286 #define BIT_INT_STATUS_DMP_POWER_SAVE 0x40 287 288 /* Bank0 REG_FIFO_CONFIG_REG */ 289 #define BIT_FIFO_MODE_BYPASS 0x00 290 #define BIT_FIFO_MODE_STREAM 0x40 291 #define BIT_FIFO_MODE_STOP_FULL 0x80 292 293 /* Bank0 REG_GYRO_ACCEL_CONFIG0 */ 294 #define BIT_ACCEL_UI_LNM_BW_2_FIR 0x00 295 #define BIT_ACCEL_UI_LNM_BW_4_IIR 0x10 296 #define BIT_ACCEL_UI_LNM_BW_5_IIR 0x20 297 #define BIT_ACCEL_UI_LNM_BW_8_IIR 0x30 298 #define BIT_ACCEL_UI_LNM_BW_10_IIR 0x40 299 #define BIT_ACCEL_UI_LNM_BW_16_IIR 0x50 300 #define BIT_ACCEL_UI_LNM_BW_20_IIR 0x60 301 #define BIT_ACCEL_UI_LNM_BW_40_IIR 0x70 302 #define BIT_ACCEL_UI_LNM_AVG_1 0xF0 303 #define BIT_ACCEL_UI_LPM_BW_2_FIR 0x00 304 #define BIT_ACCEL_UI_LPM_AVG_1 0x10 305 #define BIT_ACCEL_UI_LPM_AVG_2 0x20 306 #define BIT_ACCEL_UI_LPM_AVG_3 0x30 307 #define BIT_ACCEL_UI_LPM_AVG_4 0x40 308 #define BIT_ACCEL_UI_LPM_AVG_8 0x50 309 #define BIT_ACCEL_UI_LPM_AVG_16 0x60 310 #define BIT_ACCEL_UI_LPM_AVG_32 0x70 311 #define BIT_ACCEL_UI_LPM_AVG_64 0x80 312 #define BIT_ACCEL_UI_LPM_AVG_128 0x90 313 #define BIT_GYRO_UI_LNM_BW_2_FIR 0x00 314 #define BIT_GYRO_UI_LNM_BW_4_IIR 0x01 315 #define BIT_GYRO_UI_LNM_BW_5_IIR 0x02 316 #define BIT_GYRO_UI_LNM_BW_8_IIR 0x03 317 #define BIT_GYRO_UI_LNM_BW_10_IIR 0x04 318 #define BIT_GYRO_UI_LNM_BW_16_IIR 0x05 319 #define BIT_GYRO_UI_LNM_BW_20_IIR 0x06 320 #define BIT_GYRO_UI_LNM_BW_40_IIR 0x07 321 #define BIT_GYRO_UI_LNM_AVG_1 0xF0 322 #define BIT_GYRO_UI_LPM_BW_2_FIR 0x00 323 #define BIT_GYRO_UI_LPM_AVG_1 0x01 324 #define BIT_GYRO_UI_LPM_AVG_2 0x02 325 #define BIT_GYRO_UI_LPM_AVG_3 0x03 326 #define BIT_GYRO_UI_LPM_AVG_4 0x04 327 #define BIT_GYRO_UI_LPM_AVG_8 0x05 328 #define BIT_GYRO_UI_LPM_AVG_16 0x06 329 #define BIT_GYRO_UI_LPM_AVG_32 0x07 330 #define BIT_GYRO_UI_LPM_AVG_64 0x08 331 #define BIT_GYRO_UI_LPM_AVG_128 0x09 332 333 /* Bank0 REG_SMD_CONFIG */ 334 #define BIT_WOM_INT_MODE_OR 0x00 335 #define BIT_WOM_INT_MODE_AND 0x08 336 #define BIT_WOM_MODE_INITIAL 0x00 337 #define BIT_WOM_MODE_PREV 0x04 338 #define BIT_SMD_MODE_OFF 0x00 339 #define BIT_SMD_MODE_OLD 0x01 340 #define BIT_SMD_MODE_SHORT 0x02 341 #define BIT_SMD_MODE_LONG 0x03 342 343 /* Bank0 REG_TMST_CONFIG */ 344 #define BIT_FIFO_RAM_ISO_ENA 0x40 345 #define BIT_EN_DREG_FIFO_D2A 0x20 346 #define BIT_TMST_TO_REGS_EN 0x10 347 #define BIT_TMST_RESOL 0x08 348 #define BIT_TMST_DELTA_EN 0x04 349 #define BIT_TMST_FSYNC_EN 0x02 350 #define BIT_TMST_EN 0x01 351 352 /* Bank0 REG_APEX_CONFIG0 */ 353 #define BIT_DMP_ODR_25HZ 0x00 354 #define BIT_DMP_ODR_50HZ 0x02 355 #define BIT_DMP_ODR_100HZ 0x03 356 #define BIT_RAISE_ENABLE 0x08 357 #define BIT_TILT_ENABLE 0x10 358 #define BIT_PEDO_ENABLE 0x20 359 #define BIT_TAP_ENABLE 0x40 360 #define BIT_DMP_POWER_SAVE_EN 0x80 361 362 /* Bank0 REG_ACCEL_CONFIG0 */ 363 #define BIT_ACCEL_FSR 0xE0 364 #define BIT_ACCEL_ODR 0x0F 365 366 #define BIT_ACCEL_ODR_8000 0x03 367 #define BIT_ACCEL_ODR_4000 0x04 368 #define BIT_ACCEL_ODR_2000 0x05 369 #define BIT_ACCEL_ODR_1000 0x06 370 #define BIT_ACCEL_ODR_500 0x0F 371 #define BIT_ACCEL_ODR_200 0x07 372 #define BIT_ACCEL_ODR_100 0x08 373 #define BIT_ACCEL_ODR_50 0x09 374 #define BIT_ACCEL_ODR_25 0x0A 375 #define BIT_ACCEL_ODR_12 0x0B 376 #define BIT_ACCEL_ODR_6 0x0C 377 #define BIT_ACCEL_ODR_3 0x0D 378 #define BIT_ACCEL_ODR_1 0x0E 379 380 /* Bank0 REG_GYRO_CONFIG0 */ 381 #define BIT_GYRO_FSR 0xE0 382 #define BIT_GYRO_ODR 0x0F 383 #define BIT_GYRO_ODR_8000 0x03 384 #define BIT_GYRO_ODR_4000 0x04 385 #define BIT_GYRO_ODR_2000 0x05 386 #define BIT_GYRO_ODR_1000 0x06 387 #define BIT_GYRO_ODR_500 0x0F 388 #define BIT_GYRO_ODR_200 0x07 389 #define BIT_GYRO_ODR_100 0x08 390 #define BIT_GYRO_ODR_50 0x09 391 #define BIT_GYRO_ODR_25 0x0A 392 #define BIT_GYRO_ODR_12 0x0B 393 394 /* Bank1 REG_INTF_CONFIG5 */ 395 #define BIT_PIN9_FUNC_INT2 0x00 396 #define BIT_PIN9_FUNC_FSYNC 0x02 397 #define BIT_PIN9_FUNC_CLKIN 0x04 398 #define BIT_PIN9_FUNC_RSV 0x06 399 400 /* Bank4 REG_DRV_GYR_CFG0_REG */ 401 #define GYRO_DRV_TEST_FSMFORCE_D2A_LINEAR_START_MODE 0x0D 402 #define GYRO_DRV_TEST_FSMFORCE_D2A_STEADY_STATE_AGC_REG_MODE 0x2A 403 404 /* Bank4 REG_DRV_GYR_CFG2_REG */ 405 #define GYRO_DRV_SPARE2_D2A_EN 0x01 406 407 /* Bank4 REG_INT_SOURCE6 */ 408 #define BIT_INT_TAP_DET_INT1_EN 0x01 409 #define BIT_INT_SLEEP_DET_INT1_EN 0x02 410 #define BIT_INT_RAISE_DET_INT1_EN 0x04 411 #define BIT_INT_TILT_DET_INT1_EN 0x08 412 #define BIT_INT_STEP_CNT_OVFL_INT1_EN 0x10 413 #define BIT_INT_STEP_DET_INT1_EN 0x20 414 #define BIT_INT_DMP_POWER_SAVE_INT1_EN 0x40 415 416 /* Bank4 REG_INT_SOURCE7 */ 417 #define BIT_INT_TAP_DET_INT2_EN 0x01 418 #define BIT_INT_HIGHG_DET_INT2_EN 0x02 419 #define BIT_INT_LOWG_DET_INT2_EN 0x04 420 #define BIT_INT_TILT_DET_INT2_EN 0x80 421 #define BIT_INT_STEP_CNT_OVFL_INT2_EN 0x10 422 #define BIT_INT_STEP_DET_INT2_EN 0x20 423 #define BIT_INT_DMP_POWER_SAVE_INT2_EN 0x40 424 425 /* Bank4 REG_INT_SOURCE8 */ 426 #define BIT_INT_AGC_RDY_IBI_EN 0x01 427 #define BIT_INT_FIFO_FULL_IBI_EN 0x02 428 #define BIT_INT_FIFO_THS_IBI_EN 0x04 429 #define BIT_INT_UI_DRDY_IBI_EN 0x08 430 #define BIT_INT_PLL_RDY_IBI_EN 0x10 431 #define BIT_INT_FSYNC_IBI_EN 0x20 432 #define BIT_INT_OIS1_DRDY_IBI_EN 0x40 433 434 /* Bank4 REG_INT_SOURCE9 */ 435 #define BIT_INT_DMP_POWER_SAVE_IBI_EN 0x01 436 #define BIT_INT_WOM_X_IBI_EN 0x02 437 #define BIT_INT_WOM_Y_IBI_EN 0x04 438 #define BIT_INT_WOM_Z_IBI_EN 0x08 439 #define BIT_INT_SMD_IBI_EN 0x10 440 441 /* Bank4 REG_INT_SOURCE10 */ 442 #define BIT_INT_TAP_DET_IBI_EN 0x01 443 #define BIT_INT_HIGHG_DET_IBI_EN 0x02 444 #define BIT_INT_LOWG_DET_IBI_EN 0x04 445 #define BIT_INT_TILT_DET_IBI_EN 0x08 446 #define BIT_INT_STEP_CNT_OVFL_IBI_EN 0x10 447 #define BIT_INT_STEP_DET_IBI_EN 0x20 448 449 /* fifo data packet header */ 450 #define BIT_FIFO_HEAD_MSG 0x80 451 #define BIT_FIFO_HEAD_ACCEL 0x40 452 #define BIT_FIFO_HEAD_GYRO 0x20 453 #define BIT_FIFO_HEAD_20 0x10 454 #define BIT_FIFO_HEAD_TMSP_ODR 0x08 455 #define BIT_FIFO_HEAD_TMSP_NO_ODR 0x04 456 #define BIT_FIFO_HEAD_TMSP_FSYNC 0x0C 457 #define BIT_FIFO_HEAD_ODR_ACCEL 0x02 458 #define BIT_FIFO_HEAD_ODR_GYRO 0x01 459 460 /* data definitions */ 461 #define FIFO_PACKET_BYTE_SINGLE 8 462 #define FIFO_PACKET_BYTE_6X 16 463 #define FIFO_PACKET_BYTE_HIRES 20 464 #define FIFO_COUNT_BYTE 2 465 466 /* sensor startup time */ 467 #define INV_ICM42600_GYRO_START_TIME 100 468 #define INV_ICM42600_ACCEL_START_TIME 50 469 470 /* temperature sensor */ 471 /* scale by 100, 1LSB=1degC, 9447 */ 472 #define TEMP_SCALE 100 473 /* 25 degC */ 474 #define TEMP_OFFSET (25 * TEMP_SCALE) 475 476 #ifdef SUPPORT_RTC_MODE 477 #define BASE_SAMPLE_RATE (RTC_FREQ_HZ / 32) 478 #else 479 #define BASE_SAMPLE_RATE 1000 480 #endif 481 #define GESTURE_ACCEL_RATE 50 482 #define ESI_GYRO_RATE 1000 483 #define MPU_INIT_SENSOR_RATE_LNM 12 /* min Hz in LNM */ 484 #define MPU_INIT_SENSOR_RATE_LPM 3 /* min Hz in LPM */ 485 #define MAX_FIFO_PACKET_READ 16 486 #define HARDWARE_FIFO_SIZE 2048 487 #define FIFO_SIZE (HARDWARE_FIFO_SIZE * 7 / 8) 488 #define LEFT_OVER_BYTES 128 489 #define POWER_UP_TIME 100 490 #define REG_UP_TIME_USEC 100 491 #define IIO_BUFFER_BYTES 8 492 #define BYTES_PER_SENSOR 6 493 #define BYTES_FOR_TEMP 1 494 #define MAX_BATCH_FIFO_SIZE FIFO_SIZE 495 #define FIRST_DROP_SAMPLES_ACC_500HZ 20 496 #define FIRST_DROP_SAMPLES_ACC_200HZ 10 497 #define FIRST_DROP_SAMPLES_GYR_500HZ 20 498 #define FIRST_DROP_SAMPLES_GYR_200HZ 10 499 #define WOM_THRESHOLD 13 /* 1000 / 256 * 13 = 50.7mg */ 500 501 #define BIT_GYRO_FSR 0xE0 502 #define BIT_GYRO_ODR 0x0F 503 #define BIT_ACCEL_FSR 0xE0 504 #define BIT_ACCEL_ODR 0x0F 505 506 #define FIFO_ACCEL0_RESET_VALUE 0x80 507 #define FIFO_ACCEL1_RESET_VALUE 0x00 508 #define FIFO_GYRO0_RESET_VALUE 0x80 509 #define FIFO_GYRO1_RESET_VALUE 0x00 510 511 #define APEX_TAP 0x08 512 #define APEX_DOUBLE_TAP 0x10 513 514 /* 515 * INT configurations 516 * Polarity: 0 -> Active Low, 1 -> Active High 517 * Drive circuit: 0 -> Open Drain, 1 -> Push-Pull 518 * Mode: 0 -> Pulse, 1 -> Latch 519 */ 520 #define INT_POLARITY 1 521 #define INT_DRIVE_CIRCUIT 1 522 #define INT_MODE 0 523 524 #define ACC_LPM_MAX_RATE 500 525 #define GYR_LPM_MAX_RATE 200 526 527 enum { 528 GYRO_FS_2000DPS = 0, 529 GYRO_FS_1000DPS, 530 GYRO_FS_500DPS, 531 GYRO_FS_250DPS, 532 GYRO_FS_125DPS, 533 GYRO_FS_62DPS, 534 GYRO_FS_32DPS, 535 GYRO_FS_15DPS, 536 }; 537 538 enum { 539 ACCEL_FS_16G = 0, 540 ACCEL_FS_8G, 541 ACCEL_FS_4G, 542 ACCEL_FS_2G, 543 }; 544 545 #endif /* __SENSOR_ICM42605_ICM42605_REG__ */ 546
