Searched refs:REG32 (Results 1 – 7 of 7) sorted by relevance
179 timers[i] = REG32(p->addr); in deep_sleep_save_timers()180 REG32(p->addr) = 0; in deep_sleep_save_timers()204 REG32(p->addr) = timers[i] & ~p->restore_mask; in deep_sleep_restore_timers()
61 #define ADC_STAT(adc0) REG32((adc0) + 0x00000000U)62 #define ADC_CTL0(adc0) REG32((adc0) + 0x00000004U)63 #define ADC_CTL1(adc0) REG32((adc0) + 0x00000008U)64 #define ADC_SAMPT0(adc0) REG32((adc0) + 0x0000000CU)65 #define ADC_SAMPT1(adc0) REG32((adc0) + 0x00000010U)66 #define ADC_RSQ2(adc0) REG32((adc0) + 0x00000034U)67 #define ADC_RDATA(adc0) REG32((adc0) + 0x0000004CU)
44 #define DMA_INTF(dma) REG32(dma + 0x00UL)45 #define DMA_INTC(dma) REG32(dma + 0x04UL)46 #define DMA_CHCTL(dma, ch) REG32((dma + 0x08UL) + 0x14UL * (uint32_t)(ch))47 #define DMA_CHCNT(dma, ch) REG32((dma + 0x0CUL) + 0x14UL * (uint32_t)(ch))48 #define DMA_CHPADDR(dma, ch) REG32((dma + 0x10UL) + 0x14UL * (uint32_t)(ch))49 #define DMA_CHMADDR(dma, ch) REG32((dma + 0x14UL) + 0x14UL * (uint32_t)(ch))
44 return REG32(raddr); in descr_rd()52 REG32(raddr) = val; in descr_wr()
147 #define REG32 0x32 macro349 { REG32, REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
1359 REG32(MCHP_GIRQ_SRC_ADDR(config->bus_girq_id)) = girq_result; in espi_xec_bus_isr()1379 REG32(MCHP_GIRQ_SRC_ADDR(config->vw_girq_ids[0])) = girq_result; in espi_xec_vw_isr()1429 REG32(MCHP_GIRQ_SRC_ADDR(config->pc_girq_id)) = girq_result; in espi_xec_periph_isr()
319 REG32(MCHP_GIRQ_SRC_ADDR(config->girq_id)) = girq_result; in gpio_gpio_xec_port_isr()
