1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_can
8
9 #include <zephyr/kernel.h>
10 #include <errno.h>
11 #include <zephyr/drivers/can.h>
12 #include <zephyr/drivers/can/transceiver.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18
19 LOG_MODULE_REGISTER(can_rcar, CONFIG_CAN_LOG_LEVEL);
20
21 /* Control Register */
22 #define RCAR_CAN_CTLR 0x0840
23 /* Control Register bits */
24 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
25 #define RCAR_CAN_CTLR_BOM_ENT BIT(11) /* Automatic halt mode entry at bus-off entry */
26 #define RCAR_CAN_CTLR_SLPM BIT(10)
27 #define RCAR_CAN_CTLR_CANM_HALT BIT(9)
28 #define RCAR_CAN_CTLR_CANM_RESET BIT(8)
29 #define RCAR_CAN_CTLR_CANM_MASK (3 << 8)
30 #define RCAR_CAN_CTLR_MLM BIT(3) /* Message Lost Mode Select */
31 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
32 #define RCAR_CAN_CTLR_IDFM_MIXED BIT(2) /* Mixed ID mode */
33 #define RCAR_CAN_CTLR_MBM BIT(0) /* Mailbox Mode select */
34
35 /* Mask Register */
36 #define RCAR_CAN_MKR0 0x0430
37 #define RCAR_CAN_MKR1 0x0434
38 #define RCAR_CAN_MKR2 0x0400
39 #define RCAR_CAN_MKR3 0x0404
40 #define RCAR_CAN_MKR4 0x0408
41 #define RCAR_CAN_MKR5 0x040C
42 #define RCAR_CAN_MKR6 0x0410
43 #define RCAR_CAN_MKR7 0x0414
44 #define RCAR_CAN_MKR8 0x0418
45 #define RCAR_CAN_MKR9 0x041C
46
47 /* FIFO Received ID Compare Register 0 */
48 #define RCAR_CAN_FIDCR0 0x0420
49
50 /* FIFO Received ID Compare Register 1 */
51 #define RCAR_CAN_FIDCR1 0x0424
52
53 /* FIFO Received ID Compare Registers 0 and 1 bits */
54 #define RCAR_CAN_FIDCR_IDE BIT(31) /* ID Extension Bit */
55 #define RCAR_CAN_FIDCR_RTR BIT(30) /* RTR Bit */
56
57 /* Mask Invalid Register 0 */
58 #define RCAR_CAN_MKIVLR0 0x0438
59 /* Mask Invalid Register 1 */
60 #define RCAR_CAN_MKIVLR1 0x0428
61 /* Mailbox Interrupt Enable Registers*/
62 #define RCAR_CAN_MIER0 0x043C
63 #define RCAR_CAN_MIER1 0x042C
64 #define RCAR_CAN_MIER1_RXFIE BIT(28) /* Rx FIFO Interrupt Enable */
65 #define RCAR_CAN_MIER1_TXFIE BIT(24) /* Tx FIFO Interrupt Enable */
66
67 #define RCAR_CAN_STR 0x0842 /* Status Register */
68 #define RCAR_CAN_STR_RSTST BIT(8) /* Reset Status Bit */
69 #define RCAR_CAN_STR_HLTST BIT(9) /* Halt Status Bit */
70 #define RCAR_CAN_STR_SLPST BIT(10) /* Sleep Status Bit */
71 #define MAX_STR_READS 0x100
72
73 /* Bit Configuration Register */
74 #define RCAR_CAN_BCR 0x0844
75
76 /* Clock Select Register */
77 #define RCAR_CAN_CLKR 0x0847
78 #define RCAR_CAN_CLKR_EXT_CLOCK 0x3 /* External input clock */
79 #define RCAR_CAN_CLKR_CLKP2 0x1
80 #define RCAR_CAN_CLKR_CLKP1 0x0
81
82 /* Error Interrupt Enable Register */
83 #define RCAR_CAN_EIER 0x084C
84
85 /* Interrupt Enable Register */
86 #define RCAR_CAN_IER 0x0860
87 #define RCAR_CAN_IER_ERSIE BIT(5) /* Error Interrupt Enable Bit */
88 #define RCAR_CAN_IER_RXFIE BIT(4) /* Rx FIFO Interrupt Enable Bit */
89 #define RCAR_CAN_IER_TXFIE BIT(3) /* Tx FIFO Interrupt Enable Bit */
90
91 /* Interrupt Status Register */
92 #define RCAR_CAN_ISR 0x0861
93 #define RCAR_CAN_ISR_ERSF BIT(5) /* Error (ERS) Interrupt */
94 #define RCAR_CAN_ISR_RXFF BIT(4) /* Reception FIFO Interrupt */
95 #define RCAR_CAN_ISR_TXFF BIT(3) /* Transmission FIFO Interrupt */
96
97 /* Receive FIFO Control Register */
98 #define RCAR_CAN_RFCR 0x0848
99 #define RCAR_CAN_RFCR_RFE BIT(0) /* Receive FIFO Enable */
100 #define RCAR_CAN_RFCR_RFEST BIT(7) /* Receive FIFO Empty Flag */
101
102 /* Receive FIFO Pointer Control Register */
103 #define RCAR_CAN_RFPCR 0x0849
104
105 /* Transmit FIFO Control Register */
106 #define RCAR_CAN_TFCR 0x084A
107 #define RCAR_CAN_TFCR_TFE BIT(0) /* Transmit FIFO Enable */
108 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Msg Number Status Bits */
109 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Tx FIFO Unsent */
110
111 /* Transmit FIFO Pointer Control Register */
112 #define RCAR_CAN_TFPCR 0x084B
113
114 /* Error Code Store Register*/
115 #define RCAR_CAN_ECSR 0x0850 /* Error Code Store Register */
116 #define RCAR_CAN_ECSR_EDPM BIT(7) /* Error Display Mode Select */
117 #define RCAR_CAN_ECSR_ADEF BIT(6) /* ACK Delimiter Error Flag */
118 #define RCAR_CAN_ECSR_BE0F BIT(5) /* Bit Error (dominant) Flag */
119 #define RCAR_CAN_ECSR_BE1F BIT(4) /* Bit Error (recessive) Flag */
120 #define RCAR_CAN_ECSR_CEF BIT(3) /* CRC Error Flag */
121 #define RCAR_CAN_ECSR_AEF BIT(2) /* ACK Error Flag */
122 #define RCAR_CAN_ECSR_FEF BIT(1) /* Form Error Flag */
123 #define RCAR_CAN_ECSR_SEF BIT(0) /* Stuff Error Flag */
124
125 /* Test Control Register */
126 #define RCAR_CAN_TCR 0x0858
127 #define RCAR_CAN_TCR_TSTE BIT(0) /* Test Mode Enable Bit*/
128 #define RCAR_CAN_TCR_LISTEN_ONLY BIT(1)
129 #define RCAR_CAN_TCR_INT_LOOP (3 << 1) /* Internal loopback*/
130
131 /* Error Interrupt Factor Judge Register bits */
132 #define RCAR_CAN_EIFR 0x084D
133 #define RCAR_CAN_EIFR_BLIF BIT(7) /* Bus Lock Detect Flag */
134 #define RCAR_CAN_EIFR_OLIF BIT(6) /* Overload Frame Transmission */
135 #define RCAR_CAN_EIFR_ORIF BIT(5) /* Receive Overrun Detect Flag */
136 #define RCAR_CAN_EIFR_BORIF BIT(4) /* Bus-Off Recovery Detect Flag */
137 #define RCAR_CAN_EIFR_BOEIF BIT(3) /* Bus-Off Entry Detect Flag */
138 #define RCAR_CAN_EIFR_EPIF BIT(2) /* Error Passive Detect Flag */
139 #define RCAR_CAN_EIFR_EWIF BIT(1) /* Error Warning Detect Flag */
140 #define RCAR_CAN_EIFR_BEIF BIT(0) /* Bus Error Detect Flag */
141
142 /* Receive Error Count Register */
143 #define RCAR_CAN_RECR 0x084D
144 /* Transmit Error Count Register */
145 #define RCAR_CAN_TECR 0x084F
146
147 /* Mailbox configuration:
148 * mailbox 60 - 63 - Rx FIFO mailboxes
149 * mailbox 56 - 59 - Tx FIFO mailboxes
150 * non-FIFO mailboxes are not used
151 */
152 #define RCAR_CAN_MB_56 0x0380
153 #define RCAR_CAN_MB_60 0x03C0
154 /* DLC must be accessed as a 16 bit register */
155 #define RCAR_CAN_MB_DLC_OFFSET 0x4 /* Data length code */
156 #define RCAR_CAN_MB_DATA_OFFSET 0x6 /* Data section */
157 #define RCAR_CAN_MB_TSH_OFFSET 0x14 /* Timestamp upper byte */
158 #define RCAR_CAN_MB_TSL_OFFSET 0x15 /* Timestamp lower byte */
159 #define RCAR_CAN_FIFO_DEPTH 4
160 #define RCAR_CAN_MB_SID_SHIFT 18
161 #define RCAR_CAN_MB_RTR BIT(30)
162 #define RCAR_CAN_MB_IDE BIT(31)
163 #define RCAR_CAN_MB_SID_MASK 0x1FFC0000
164 #define RCAR_CAN_MB_EID_MASK 0x1FFFFFFF
165
166 typedef void (*init_func_t)(const struct device *dev);
167
168 struct can_rcar_cfg {
169 uint32_t reg_addr;
170 int reg_size;
171 init_func_t init_func;
172 const struct device *clock_dev;
173 struct rcar_cpg_clk mod_clk;
174 struct rcar_cpg_clk bus_clk;
175 uint32_t bus_speed;
176 uint8_t sjw;
177 uint8_t prop_seg;
178 uint8_t phase_seg1;
179 uint8_t phase_seg2;
180 uint16_t sample_point;
181 const struct pinctrl_dev_config *pcfg;
182 const struct device *phy;
183 uint32_t max_bitrate;
184 };
185
186 struct can_rcar_tx_cb {
187 can_tx_callback_t cb;
188 void *cb_arg;
189 };
190
191 struct can_rcar_data {
192 struct k_mutex inst_mutex;
193 struct k_sem tx_sem;
194 struct can_rcar_tx_cb tx_cb[RCAR_CAN_FIFO_DEPTH];
195 uint8_t tx_head;
196 uint8_t tx_tail;
197 uint8_t tx_unsent;
198 struct k_mutex rx_mutex;
199 can_rx_callback_t rx_callback[CONFIG_CAN_RCAR_MAX_FILTER];
200 void *rx_callback_arg[CONFIG_CAN_RCAR_MAX_FILTER];
201 struct can_filter filter[CONFIG_CAN_RCAR_MAX_FILTER];
202 can_state_change_callback_t state_change_cb;
203 void *state_change_cb_data;
204 enum can_state state;
205 bool started;
206 };
207
can_rcar_read16(const struct can_rcar_cfg * config,uint32_t offs)208 static inline uint16_t can_rcar_read16(const struct can_rcar_cfg *config,
209 uint32_t offs)
210 {
211 return sys_read16(config->reg_addr + offs);
212 }
213
can_rcar_write16(const struct can_rcar_cfg * config,uint32_t offs,uint16_t value)214 static inline void can_rcar_write16(const struct can_rcar_cfg *config,
215 uint32_t offs, uint16_t value)
216 {
217 sys_write16(value, config->reg_addr + offs);
218 }
219
can_rcar_tx_done(const struct device * dev,uint8_t err)220 static void can_rcar_tx_done(const struct device *dev, uint8_t err)
221 {
222 struct can_rcar_data *data = dev->data;
223 struct can_rcar_tx_cb *tx_cb;
224
225 tx_cb = &data->tx_cb[data->tx_tail];
226 data->tx_tail++;
227 if (data->tx_tail >= RCAR_CAN_FIFO_DEPTH) {
228 data->tx_tail = 0;
229 }
230
231 data->tx_unsent--;
232 tx_cb->cb(dev, err, tx_cb->cb_arg);
233 k_sem_give(&data->tx_sem);
234 }
235
can_rcar_get_error_count(const struct can_rcar_cfg * config,struct can_bus_err_cnt * err_cnt)236 static void can_rcar_get_error_count(const struct can_rcar_cfg *config,
237 struct can_bus_err_cnt *err_cnt)
238 {
239 err_cnt->tx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_TECR);
240 err_cnt->rx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_RECR);
241 }
242
can_rcar_state_change(const struct device * dev,uint32_t newstate)243 static void can_rcar_state_change(const struct device *dev, uint32_t newstate)
244 {
245 const struct can_rcar_cfg *config = dev->config;
246 struct can_rcar_data *data = dev->data;
247 const can_state_change_callback_t cb = data->state_change_cb;
248 void *state_change_cb_data = data->state_change_cb_data;
249 struct can_bus_err_cnt err_cnt;
250
251 if (data->state == newstate) {
252 return;
253 }
254
255 LOG_DBG("Can state change new: %u old:%u\n", newstate, data->state);
256
257 data->state = newstate;
258
259 if (cb == NULL) {
260 return;
261 }
262 can_rcar_get_error_count(config, &err_cnt);
263 cb(dev, newstate, err_cnt, state_change_cb_data);
264 }
265
can_rcar_error(const struct device * dev)266 static void can_rcar_error(const struct device *dev)
267 {
268 const struct can_rcar_cfg *config = dev->config;
269 uint8_t eifr, ecsr;
270
271 eifr = sys_read8(config->reg_addr + RCAR_CAN_EIFR);
272
273 if (eifr & RCAR_CAN_EIFR_BEIF) {
274
275 ecsr = sys_read8(config->reg_addr + RCAR_CAN_ECSR);
276 if (ecsr & RCAR_CAN_ECSR_ADEF) {
277 CAN_STATS_ACK_ERROR_INC(dev);
278 sys_write8((uint8_t)~RCAR_CAN_ECSR_ADEF,
279 config->reg_addr + RCAR_CAN_ECSR);
280 }
281 if (ecsr & RCAR_CAN_ECSR_BE0F) {
282 CAN_STATS_BIT0_ERROR_INC(dev);
283 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE0F,
284 config->reg_addr + RCAR_CAN_ECSR);
285 }
286 if (ecsr & RCAR_CAN_ECSR_BE1F) {
287 CAN_STATS_BIT1_ERROR_INC(dev);
288 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE1F,
289 config->reg_addr + RCAR_CAN_ECSR);
290 }
291 if (ecsr & RCAR_CAN_ECSR_CEF) {
292 CAN_STATS_CRC_ERROR_INC(dev);
293 sys_write8((uint8_t)~RCAR_CAN_ECSR_CEF,
294 config->reg_addr + RCAR_CAN_ECSR);
295 }
296 if (ecsr & RCAR_CAN_ECSR_AEF) {
297 CAN_STATS_ACK_ERROR_INC(dev);
298 sys_write8((uint8_t)~RCAR_CAN_ECSR_AEF,
299 config->reg_addr + RCAR_CAN_ECSR);
300 }
301 if (ecsr & RCAR_CAN_ECSR_FEF) {
302 CAN_STATS_FORM_ERROR_INC(dev);
303 sys_write8((uint8_t)~RCAR_CAN_ECSR_FEF,
304 config->reg_addr + RCAR_CAN_ECSR);
305 }
306 if (ecsr & RCAR_CAN_ECSR_SEF) {
307 CAN_STATS_STUFF_ERROR_INC(dev);
308 sys_write8((uint8_t)~RCAR_CAN_ECSR_SEF,
309 config->reg_addr + RCAR_CAN_ECSR);
310 }
311
312 sys_write8((uint8_t)~RCAR_CAN_EIFR_BEIF,
313 config->reg_addr + RCAR_CAN_EIFR);
314 }
315 if (eifr & RCAR_CAN_EIFR_EWIF) {
316 LOG_DBG("Error warning interrupt\n");
317 /* Clear interrupt condition */
318 sys_write8((uint8_t)~RCAR_CAN_EIFR_EWIF,
319 config->reg_addr + RCAR_CAN_EIFR);
320 can_rcar_state_change(dev, CAN_STATE_ERROR_WARNING);
321 }
322 if (eifr & RCAR_CAN_EIFR_EPIF) {
323 LOG_DBG("Error passive interrupt\n");
324 /* Clear interrupt condition */
325 sys_write8((uint8_t)~RCAR_CAN_EIFR_EPIF,
326 config->reg_addr + RCAR_CAN_EIFR);
327 can_rcar_state_change(dev, CAN_STATE_ERROR_PASSIVE);
328 }
329 if (eifr & RCAR_CAN_EIFR_BORIF) {
330 LOG_DBG("Bus-off recovery interrupt\n");
331 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
332 /* Clear interrupt condition */
333 sys_write8((uint8_t)~RCAR_CAN_EIFR_BORIF,
334 config->reg_addr + RCAR_CAN_EIFR);
335 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
336 }
337 if (eifr & RCAR_CAN_EIFR_BOEIF) {
338 LOG_DBG("Bus-off entry interrupt\n");
339 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
340 /* Clear interrupt condition */
341 sys_write8((uint8_t)~RCAR_CAN_EIFR_BOEIF,
342 config->reg_addr + RCAR_CAN_EIFR);
343 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
344 }
345 if (eifr & RCAR_CAN_EIFR_ORIF) {
346 LOG_DBG("Receive overrun error interrupt\n");
347 CAN_STATS_RX_OVERRUN_INC(dev);
348 sys_write8((uint8_t)~RCAR_CAN_EIFR_ORIF,
349 config->reg_addr + RCAR_CAN_EIFR);
350 }
351 if (eifr & RCAR_CAN_EIFR_OLIF) {
352 LOG_DBG("Overload Frame Transmission error interrupt\n");
353 sys_write8((uint8_t)~RCAR_CAN_EIFR_OLIF,
354 config->reg_addr + RCAR_CAN_EIFR);
355 }
356 if (eifr & RCAR_CAN_EIFR_BLIF) {
357 LOG_DBG("Bus lock detected interrupt\n");
358 sys_write8((uint8_t)~RCAR_CAN_EIFR_BLIF,
359 config->reg_addr + RCAR_CAN_EIFR);
360 }
361 }
362
can_rcar_rx_filter_isr(const struct device * dev,struct can_rcar_data * data,const struct can_frame * frame)363 static void can_rcar_rx_filter_isr(const struct device *dev,
364 struct can_rcar_data *data,
365 const struct can_frame *frame)
366 {
367 struct can_frame tmp_frame;
368 uint8_t i;
369
370 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
371 if (data->rx_callback[i] == NULL) {
372 continue;
373 }
374
375 if (!can_frame_matches_filter(frame, &data->filter[i])) {
376 continue; /* filter did not match */
377 }
378 /* Make a temporary copy in case the user
379 * modifies the message.
380 */
381 tmp_frame = *frame;
382 data->rx_callback[i](dev, &tmp_frame, data->rx_callback_arg[i]);
383 }
384 }
385
can_rcar_rx_isr(const struct device * dev)386 static void can_rcar_rx_isr(const struct device *dev)
387 {
388 const struct can_rcar_cfg *config = dev->config;
389 struct can_rcar_data *data = dev->data;
390 struct can_frame frame = {0};
391 uint32_t val;
392 int i;
393
394 val = sys_read32(config->reg_addr + RCAR_CAN_MB_60);
395 if (val & RCAR_CAN_MB_IDE) {
396 frame.flags |= CAN_FRAME_IDE;
397 frame.id = val & RCAR_CAN_MB_EID_MASK;
398 } else {
399 frame.id = (val & RCAR_CAN_MB_SID_MASK) >> RCAR_CAN_MB_SID_SHIFT;
400 }
401
402 frame.dlc = sys_read16(config->reg_addr +
403 RCAR_CAN_MB_60 + RCAR_CAN_MB_DLC_OFFSET) & 0xF;
404
405 /* Be paranoid doc states that any value greater than 8
406 * should be considered as 8 bytes.
407 */
408 if (frame.dlc > CAN_MAX_DLC) {
409 frame.dlc = CAN_MAX_DLC;
410 }
411
412 if (val & RCAR_CAN_MB_RTR) {
413 frame.flags |= CAN_FRAME_RTR;
414 } else {
415 for (i = 0; i < frame.dlc; i++) {
416 frame.data[i] = sys_read8(config->reg_addr +
417 RCAR_CAN_MB_60 + RCAR_CAN_MB_DATA_OFFSET + i);
418 }
419 }
420 #if defined(CONFIG_CAN_RX_TIMESTAMP)
421 /* read upper byte */
422 frame.timestamp = sys_read8(config->reg_addr +
423 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSH_OFFSET) << 8;
424 /* and then read lower byte */
425 frame.timestamp |= sys_read8(config->reg_addr +
426 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSL_OFFSET);
427 #endif
428 /* Increment CPU side pointer */
429 sys_write8(0xff, config->reg_addr + RCAR_CAN_RFPCR);
430
431 can_rcar_rx_filter_isr(dev, data, &frame);
432 }
433
can_rcar_isr(const struct device * dev)434 static void can_rcar_isr(const struct device *dev)
435 {
436 const struct can_rcar_cfg *config = dev->config;
437 struct can_rcar_data *data = dev->data;
438 uint8_t isr, unsent;
439
440 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
441 if (isr & RCAR_CAN_ISR_ERSF) {
442 /* Clear the Error interrupt */
443 isr &= ~RCAR_CAN_ISR_ERSF;
444 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
445 can_rcar_error(dev);
446 }
447 if (isr & RCAR_CAN_ISR_TXFF) {
448 /* Check for sent messages */
449 while (1) {
450 unsent = sys_read8(config->reg_addr + RCAR_CAN_TFCR);
451 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
452 RCAR_CAN_TFCR_TFUST_SHIFT;
453 if (data->tx_unsent <= unsent) {
454 break;
455 }
456 can_rcar_tx_done(dev, 0);
457 }
458
459 /* Clear the Tx interrupt */
460 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
461 isr &= ~RCAR_CAN_ISR_TXFF;
462 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
463 }
464 if (isr & RCAR_CAN_ISR_RXFF) {
465 /* while there is unread messages */
466 while (!(sys_read8(config->reg_addr + RCAR_CAN_RFCR)
467 & RCAR_CAN_RFCR_RFEST)) {
468 can_rcar_rx_isr(dev);
469 }
470 /* Clear the Rx interrupt */
471 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
472 isr &= ~RCAR_CAN_ISR_RXFF;
473 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
474 }
475 }
476
can_rcar_leave_sleep_mode(const struct can_rcar_cfg * config)477 static int can_rcar_leave_sleep_mode(const struct can_rcar_cfg *config)
478 {
479 uint16_t ctlr, str;
480 int i;
481
482 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
483 ctlr &= ~RCAR_CAN_CTLR_SLPM;
484 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
485 for (i = 0; i < MAX_STR_READS; i++) {
486 str = can_rcar_read16(config, RCAR_CAN_STR);
487 if (!(str & RCAR_CAN_STR_SLPST)) {
488 return 0;
489 }
490 }
491 return -EAGAIN;
492 }
493
can_rcar_enter_reset_mode(const struct can_rcar_cfg * config,bool force)494 static int can_rcar_enter_reset_mode(const struct can_rcar_cfg *config, bool force)
495 {
496 uint16_t ctlr;
497 int i;
498
499 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
500 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
501 ctlr |= RCAR_CAN_CTLR_CANM_RESET;
502 if (force) {
503 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
504 }
505 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
506 for (i = 0; i < MAX_STR_READS; i++) {
507 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_RSTST) {
508 return 0;
509 }
510 }
511 return -EAGAIN;
512 }
513
can_rcar_enter_halt_mode(const struct can_rcar_cfg * config)514 static int can_rcar_enter_halt_mode(const struct can_rcar_cfg *config)
515 {
516 uint16_t ctlr;
517 int i;
518
519 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
520 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
521 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
522 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
523
524 /* Wait for controller to apply high bit timing settings */
525 k_usleep(1);
526
527 for (i = 0; i < MAX_STR_READS; i++) {
528 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_HLTST) {
529 return 0;
530 }
531 }
532
533 return -EAGAIN;
534 }
535
can_rcar_enter_operation_mode(const struct can_rcar_cfg * config)536 static int can_rcar_enter_operation_mode(const struct can_rcar_cfg *config)
537 {
538 uint16_t ctlr, str;
539 int i;
540
541 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
542 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
543 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
544
545 /* Wait for controller to apply high bit timing settings */
546 k_usleep(1);
547
548 for (i = 0; i < MAX_STR_READS; i++) {
549 str = can_rcar_read16(config, RCAR_CAN_STR);
550 if (!(str & RCAR_CAN_CTLR_CANM_MASK)) {
551 break;
552 }
553 }
554
555 if (i == MAX_STR_READS) {
556 return -EAGAIN;
557 }
558
559 /* Enable Rx and Tx FIFO */
560 sys_write8(RCAR_CAN_RFCR_RFE, config->reg_addr + RCAR_CAN_RFCR);
561 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
562
563 return 0;
564 }
565
can_rcar_get_capabilities(const struct device * dev,can_mode_t * cap)566 static int can_rcar_get_capabilities(const struct device *dev, can_mode_t *cap)
567 {
568 ARG_UNUSED(dev);
569
570 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
571
572 return 0;
573 }
574
can_rcar_start(const struct device * dev)575 static int can_rcar_start(const struct device *dev)
576 {
577 const struct can_rcar_cfg *config = dev->config;
578 struct can_rcar_data *data = dev->data;
579 int ret;
580
581 if (data->started) {
582 return -EALREADY;
583 }
584
585 if (config->phy != NULL) {
586 ret = can_transceiver_enable(config->phy);
587 if (ret != 0) {
588 LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
589 return ret;
590 }
591 }
592
593 k_mutex_lock(&data->inst_mutex, K_FOREVER);
594
595 CAN_STATS_RESET(dev);
596
597 ret = can_rcar_enter_operation_mode(config);
598 if (ret != 0) {
599 LOG_ERR("failed to enter operation mode (err %d)", ret);
600
601 if (config->phy != NULL) {
602 /* Attempt to disable the CAN transceiver in case of error */
603 (void)can_transceiver_disable(config->phy);
604 }
605 } else {
606 data->started = true;
607 }
608
609 k_mutex_unlock(&data->inst_mutex);
610
611 return ret;
612 }
613
can_rcar_stop(const struct device * dev)614 static int can_rcar_stop(const struct device *dev)
615 {
616 const struct can_rcar_cfg *config = dev->config;
617 struct can_rcar_data *data = dev->data;
618 int ret;
619
620 if (!data->started) {
621 return -EALREADY;
622 }
623
624 k_mutex_lock(&data->inst_mutex, K_FOREVER);
625
626 ret = can_rcar_enter_halt_mode(config);
627 if (ret != 0) {
628 LOG_ERR("failed to enter halt mode (err %d)", ret);
629 k_mutex_unlock(&data->inst_mutex);
630 return ret;
631 }
632
633 data->started = false;
634
635 k_mutex_unlock(&data->inst_mutex);
636
637 if (config->phy != NULL) {
638 ret = can_transceiver_disable(config->phy);
639 if (ret != 0) {
640 LOG_ERR("failed to disable CAN transceiver (err %d)", ret);
641 return ret;
642 }
643 }
644
645 /* Resetting TX FIFO, emptying it */
646 sys_write8((uint8_t)~RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
647 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
648
649 /* Empty TX msgq, returning an error for each message */
650 while (data->tx_unsent) {
651 can_rcar_tx_done(dev, -ENETDOWN);
652 }
653
654 return 0;
655 }
656
can_rcar_set_mode(const struct device * dev,can_mode_t mode)657 static int can_rcar_set_mode(const struct device *dev, can_mode_t mode)
658 {
659 const struct can_rcar_cfg *config = dev->config;
660 struct can_rcar_data *data = dev->data;
661 uint8_t tcr = 0;
662 int ret = 0;
663
664 if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) != 0) {
665 LOG_ERR("Unsupported mode: 0x%08x", mode);
666 return -ENOTSUP;
667 }
668
669 if (data->started) {
670 return -EBUSY;
671 }
672
673 k_mutex_lock(&data->inst_mutex, K_FOREVER);
674
675 if ((mode & (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) ==
676 (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) {
677 LOG_ERR("Combination of loopback and listenonly modes not supported");
678 ret = -ENOTSUP;
679 goto unlock;
680 } else if ((mode & CAN_MODE_LOOPBACK) != 0) {
681 /* Loopback mode */
682 tcr = RCAR_CAN_TCR_INT_LOOP | RCAR_CAN_TCR_TSTE;
683 } else if ((mode & CAN_MODE_LISTENONLY) != 0) {
684 /* Listen-only mode */
685 tcr = RCAR_CAN_TCR_LISTEN_ONLY | RCAR_CAN_TCR_TSTE;
686 } else {
687 /* Normal mode */
688 tcr = 0;
689 }
690
691 sys_write8(tcr, config->reg_addr + RCAR_CAN_TCR);
692
693 unlock:
694 k_mutex_unlock(&data->inst_mutex);
695
696 return ret;
697 }
698
699 /* Bit Configuration Register settings */
700 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
701 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
702 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
703 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
704
can_rcar_set_bittiming(const struct can_rcar_cfg * config,const struct can_timing * timing)705 static void can_rcar_set_bittiming(const struct can_rcar_cfg *config,
706 const struct can_timing *timing)
707 {
708 uint32_t bcr;
709
710 bcr = RCAR_CAN_BCR_TSEG1(timing->phase_seg1 + timing->prop_seg - 1) |
711 RCAR_CAN_BCR_BPR(timing->prescaler - 1) |
712 RCAR_CAN_BCR_SJW(timing->sjw - 1) |
713 RCAR_CAN_BCR_TSEG2(timing->phase_seg2 - 1);
714
715 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
716 * All the registers are big-endian but they get byte-swapped on 32-bit
717 * read/write (but not on 8-bit, contrary to the manuals)...
718 */
719 sys_write32((bcr << 8) | RCAR_CAN_CLKR_CLKP2,
720 config->reg_addr + RCAR_CAN_BCR);
721 }
722
can_rcar_set_timing(const struct device * dev,const struct can_timing * timing)723 static int can_rcar_set_timing(const struct device *dev,
724 const struct can_timing *timing)
725 {
726 const struct can_rcar_cfg *config = dev->config;
727 struct can_rcar_data *data = dev->data;
728 int ret = 0;
729
730 struct reg_backup {
731 uint32_t address;
732 uint8_t value;
733 };
734
735 struct reg_backup regs[3] = { { RCAR_CAN_TCR, 0 }, { RCAR_CAN_TFCR, 0 }
736 , { RCAR_CAN_RFCR, 0 } };
737
738 if (data->started) {
739 return -EBUSY;
740 }
741
742 k_mutex_lock(&data->inst_mutex, K_FOREVER);
743
744 /* Changing bittiming should be done in reset mode.
745 * Switching to reset mode is resetting loopback mode (TCR),
746 * transmit and receive FIFOs (TFCR and RFCR).
747 * Storing these reg values to restore them once back in halt mode.
748 */
749 for (int i = 0; i < 3; i++) {
750 regs[i].value = sys_read8(config->reg_addr + regs[i].address);
751 }
752
753 /* Switching to reset mode */
754 ret = can_rcar_enter_reset_mode(config, true);
755 if (ret != 0) {
756 goto unlock;
757 }
758
759 /* Setting bit timing */
760 can_rcar_set_bittiming(config, timing);
761
762 /* Restoring registers must be done in halt mode */
763 ret = can_rcar_enter_halt_mode(config);
764 if (ret) {
765 goto unlock;
766 }
767
768 /* Restoring registers */
769 for (int i = 0; i < 3; i++) {
770 sys_write8(regs[i].value, config->reg_addr + regs[i].address);
771 }
772
773 unlock:
774 k_mutex_unlock(&data->inst_mutex);
775 return ret;
776 }
777
can_rcar_set_state_change_callback(const struct device * dev,can_state_change_callback_t cb,void * user_data)778 static void can_rcar_set_state_change_callback(const struct device *dev,
779 can_state_change_callback_t cb,
780 void *user_data)
781 {
782 struct can_rcar_data *data = dev->data;
783
784 data->state_change_cb = cb;
785 data->state_change_cb_data = user_data;
786 }
787
can_rcar_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)788 static int can_rcar_get_state(const struct device *dev, enum can_state *state,
789 struct can_bus_err_cnt *err_cnt)
790 {
791 const struct can_rcar_cfg *config = dev->config;
792 struct can_rcar_data *data = dev->data;
793
794 if (state != NULL) {
795 if (!data->started) {
796 *state = CAN_STATE_STOPPED;
797 } else {
798 *state = data->state;
799 }
800 }
801
802 if (err_cnt != NULL) {
803 can_rcar_get_error_count(config, err_cnt);
804 }
805
806 return 0;
807 }
808
809 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
can_rcar_recover(const struct device * dev,k_timeout_t timeout)810 static int can_rcar_recover(const struct device *dev, k_timeout_t timeout)
811 {
812 const struct can_rcar_cfg *config = dev->config;
813 struct can_rcar_data *data = dev->data;
814 int64_t start_time;
815 int ret;
816
817 if (!data->started) {
818 return -ENETDOWN;
819 }
820
821 if (data->state != CAN_STATE_BUS_OFF) {
822 return 0;
823 }
824
825 if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) {
826 return -EAGAIN;
827 }
828
829 start_time = k_uptime_ticks();
830 while (data->state == CAN_STATE_BUS_OFF) {
831 ret = can_rcar_enter_operation_mode(config);
832 if (ret != 0) {
833 goto done;
834 }
835
836 if (!K_TIMEOUT_EQ(timeout, K_FOREVER) &&
837 k_uptime_ticks() - start_time >= timeout.ticks) {
838 ret = -EAGAIN;
839 goto done;
840 }
841 }
842
843 done:
844 k_mutex_unlock(&data->inst_mutex);
845 return ret;
846 }
847 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
848
can_rcar_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)849 static int can_rcar_send(const struct device *dev, const struct can_frame *frame,
850 k_timeout_t timeout, can_tx_callback_t callback,
851 void *user_data)
852 {
853 const struct can_rcar_cfg *config = dev->config;
854 struct can_rcar_data *data = dev->data;
855 struct can_rcar_tx_cb *tx_cb;
856 uint32_t identifier;
857 int i;
858
859 LOG_DBG("Sending %d bytes on %s. "
860 "Id: 0x%x, "
861 "ID type: %s, "
862 "Remote Frame: %s"
863 , frame->dlc, dev->name
864 , frame->id
865 , (frame->flags & CAN_FRAME_IDE) != 0 ?
866 "extended" : "standard"
867 , (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no");
868
869 __ASSERT_NO_MSG(callback != NULL);
870 __ASSERT(frame->dlc == 0U || frame->data != NULL, "Dataptr is null");
871
872 if (frame->dlc > CAN_MAX_DLC) {
873 LOG_ERR("DLC of %d exceeds maximum (%d)",
874 frame->dlc, CAN_MAX_DLC);
875 return -EINVAL;
876 }
877
878 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) {
879 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
880 return -ENOTSUP;
881 }
882
883 if (!data->started) {
884 return -ENETDOWN;
885 }
886
887 /* Wait for a slot into the tx FIFO */
888 if (k_sem_take(&data->tx_sem, timeout) != 0) {
889 return -EAGAIN;
890 }
891
892 k_mutex_lock(&data->inst_mutex, K_FOREVER);
893 tx_cb = &data->tx_cb[data->tx_head];
894 tx_cb->cb = callback;
895 tx_cb->cb_arg = user_data;
896
897 data->tx_head++;
898 if (data->tx_head >= RCAR_CAN_FIFO_DEPTH) {
899 data->tx_head = 0;
900 }
901
902 if ((frame->flags & CAN_FRAME_IDE) != 0) {
903 identifier = frame->id | RCAR_CAN_MB_IDE;
904 } else {
905 identifier = frame->id << RCAR_CAN_MB_SID_SHIFT;
906 }
907
908 if ((frame->flags & CAN_FRAME_RTR) != 0) {
909 identifier |= RCAR_CAN_MB_RTR;
910 }
911
912 sys_write32(identifier, config->reg_addr + RCAR_CAN_MB_56);
913
914 sys_write16(frame->dlc, config->reg_addr
915 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DLC_OFFSET);
916
917 if ((frame->flags & CAN_FRAME_RTR) == 0) {
918 for (i = 0; i < frame->dlc; i++) {
919 sys_write8(frame->data[i], config->reg_addr
920 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DATA_OFFSET + i);
921 }
922 }
923
924 compiler_barrier();
925 data->tx_unsent++;
926 /* Start Tx: increment the CPU-side pointer for the transmit FIFO
927 * to the next mailbox location
928 */
929 sys_write8(0xff, config->reg_addr + RCAR_CAN_TFPCR);
930
931 k_mutex_unlock(&data->inst_mutex);
932
933 return 0;
934 }
935
can_rcar_add_rx_filter_unlocked(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)936 static inline int can_rcar_add_rx_filter_unlocked(const struct device *dev,
937 can_rx_callback_t cb,
938 void *cb_arg,
939 const struct can_filter *filter)
940 {
941 struct can_rcar_data *data = dev->data;
942 int i;
943
944 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
945 if (data->rx_callback[i] == NULL) {
946 data->rx_callback_arg[i] = cb_arg;
947 data->filter[i] = *filter;
948 compiler_barrier();
949 data->rx_callback[i] = cb;
950 return i;
951 }
952 }
953
954 return -ENOSPC;
955 }
956
can_rcar_add_rx_filter(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)957 static int can_rcar_add_rx_filter(const struct device *dev, can_rx_callback_t cb,
958 void *cb_arg, const struct can_filter *filter)
959 {
960 struct can_rcar_data *data = dev->data;
961 int filter_id;
962
963 if ((filter->flags & ~(CAN_FILTER_IDE | CAN_FILTER_DATA)) != 0) {
964 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
965 return -ENOTSUP;
966 }
967
968 k_mutex_lock(&data->rx_mutex, K_FOREVER);
969 filter_id = can_rcar_add_rx_filter_unlocked(dev, cb, cb_arg, filter);
970 k_mutex_unlock(&data->rx_mutex);
971 return filter_id;
972 }
973
can_rcar_remove_rx_filter(const struct device * dev,int filter_id)974 static void can_rcar_remove_rx_filter(const struct device *dev, int filter_id)
975 {
976 struct can_rcar_data *data = dev->data;
977
978 if (filter_id >= CONFIG_CAN_RCAR_MAX_FILTER) {
979 return;
980 }
981
982 k_mutex_lock(&data->rx_mutex, K_FOREVER);
983 compiler_barrier();
984 data->rx_callback[filter_id] = NULL;
985 k_mutex_unlock(&data->rx_mutex);
986 }
987
can_rcar_init(const struct device * dev)988 static int can_rcar_init(const struct device *dev)
989 {
990 const struct can_rcar_cfg *config = dev->config;
991 struct can_rcar_data *data = dev->data;
992 struct can_timing timing = { 0 };
993 int ret;
994 uint16_t ctlr;
995
996 k_mutex_init(&data->inst_mutex);
997 k_mutex_init(&data->rx_mutex);
998 k_sem_init(&data->tx_sem, RCAR_CAN_FIFO_DEPTH, RCAR_CAN_FIFO_DEPTH);
999
1000 data->tx_head = 0;
1001 data->tx_tail = 0;
1002 data->tx_unsent = 0;
1003
1004 memset(data->rx_callback, 0, sizeof(data->rx_callback));
1005 data->state = CAN_STATE_ERROR_ACTIVE;
1006 data->state_change_cb = NULL;
1007 data->state_change_cb_data = NULL;
1008
1009 if (config->phy != NULL) {
1010 if (!device_is_ready(config->phy)) {
1011 LOG_ERR("CAN transceiver not ready");
1012 return -ENODEV;
1013 }
1014 }
1015
1016 if (!device_is_ready(config->clock_dev)) {
1017 LOG_ERR("clock control device not ready");
1018 return -ENODEV;
1019 }
1020
1021 /* Configure dt provided device signals when available */
1022 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1023 if (ret < 0) {
1024 return ret;
1025 }
1026
1027 /* reset the registers */
1028 ret = clock_control_off(config->clock_dev,
1029 (clock_control_subsys_t)&config->mod_clk);
1030 if (ret < 0) {
1031 return ret;
1032 }
1033
1034 ret = clock_control_on(config->clock_dev,
1035 (clock_control_subsys_t)&config->mod_clk);
1036 if (ret < 0) {
1037 return ret;
1038 }
1039
1040 ret = clock_control_on(config->clock_dev,
1041 (clock_control_subsys_t)&config->bus_clk);
1042 if (ret < 0) {
1043 return ret;
1044 }
1045
1046 ret = can_rcar_enter_reset_mode(config, false);
1047 __ASSERT(!ret, "Fail to set CAN controller to reset mode");
1048 if (ret) {
1049 return ret;
1050 }
1051
1052 ret = can_rcar_leave_sleep_mode(config);
1053 __ASSERT(!ret, "Fail to leave CAN controller from sleep mode");
1054 if (ret) {
1055 return ret;
1056 }
1057
1058 if (config->sample_point) {
1059 ret = can_calc_timing(dev, &timing, config->bus_speed,
1060 config->sample_point);
1061 if (ret == -EINVAL) {
1062 LOG_ERR("Can't find timing for given param");
1063 return -EIO;
1064 }
1065 LOG_DBG("Presc: %d, TS1: %d, TS2: %d",
1066 timing.prescaler, timing.phase_seg1, timing.phase_seg2);
1067 LOG_DBG("Sample-point err : %d", ret);
1068 } else {
1069 timing.sjw = config->sjw;
1070 timing.prop_seg = config->prop_seg;
1071 timing.phase_seg1 = config->phase_seg1;
1072 timing.phase_seg2 = config->phase_seg2;
1073 ret = can_calc_prescaler(dev, &timing, config->bus_speed);
1074 if (ret) {
1075 LOG_WRN("Bitrate error: %d", ret);
1076 }
1077 }
1078
1079 ret = can_set_timing(dev, &timing);
1080 if (ret) {
1081 return ret;
1082 }
1083
1084 ret = can_rcar_set_mode(dev, CAN_MODE_NORMAL);
1085 if (ret) {
1086 return ret;
1087 }
1088
1089 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
1090 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
1091 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
1092 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically at bus-off */
1093 #endif
1094 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
1095 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
1096 ctlr &= ~RCAR_CAN_CTLR_SLPM; /* Clear CAN Sleep mode */
1097 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
1098
1099 /* Accept all SID and EID */
1100 sys_write32(0, config->reg_addr + RCAR_CAN_MKR8);
1101 sys_write32(0, config->reg_addr + RCAR_CAN_MKR9);
1102 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
1103 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR0);
1104 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR1);
1105 /* Accept standard and extended ID frames, but not
1106 * remote frame.
1107 */
1108 sys_write32(0, config->reg_addr + RCAR_CAN_FIDCR0);
1109 sys_write32(RCAR_CAN_FIDCR_IDE,
1110 config->reg_addr + RCAR_CAN_FIDCR1);
1111
1112 /* Enable and configure FIFO mailbox interrupts Rx and Tx */
1113 sys_write32(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE,
1114 config->reg_addr + RCAR_CAN_MIER1);
1115
1116 sys_write8(RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | RCAR_CAN_IER_TXFIE,
1117 config->reg_addr + RCAR_CAN_IER);
1118
1119 /* Accumulate error codes */
1120 sys_write8(RCAR_CAN_ECSR_EDPM, config->reg_addr + RCAR_CAN_ECSR);
1121
1122 /* Enable interrupts for all type of errors */
1123 sys_write8(0xFF, config->reg_addr + RCAR_CAN_EIER);
1124
1125 config->init_func(dev);
1126
1127 return 0;
1128 }
1129
can_rcar_get_core_clock(const struct device * dev,uint32_t * rate)1130 static int can_rcar_get_core_clock(const struct device *dev, uint32_t *rate)
1131 {
1132 const struct can_rcar_cfg *config = dev->config;
1133
1134 *rate = config->bus_clk.rate;
1135 return 0;
1136 }
1137
can_rcar_get_max_filters(const struct device * dev,bool ide)1138 static int can_rcar_get_max_filters(const struct device *dev, bool ide)
1139 {
1140 ARG_UNUSED(ide);
1141
1142 return CONFIG_CAN_RCAR_MAX_FILTER;
1143 }
1144
can_rcar_get_max_bitrate(const struct device * dev,uint32_t * max_bitrate)1145 static int can_rcar_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate)
1146 {
1147 const struct can_rcar_cfg *config = dev->config;
1148
1149 *max_bitrate = config->max_bitrate;
1150
1151 return 0;
1152 }
1153
1154 static const struct can_driver_api can_rcar_driver_api = {
1155 .get_capabilities = can_rcar_get_capabilities,
1156 .start = can_rcar_start,
1157 .stop = can_rcar_stop,
1158 .set_mode = can_rcar_set_mode,
1159 .set_timing = can_rcar_set_timing,
1160 .send = can_rcar_send,
1161 .add_rx_filter = can_rcar_add_rx_filter,
1162 .remove_rx_filter = can_rcar_remove_rx_filter,
1163 .get_state = can_rcar_get_state,
1164 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
1165 .recover = can_rcar_recover,
1166 #endif
1167 .set_state_change_callback = can_rcar_set_state_change_callback,
1168 .get_core_clock = can_rcar_get_core_clock,
1169 .get_max_filters = can_rcar_get_max_filters,
1170 .get_max_bitrate = can_rcar_get_max_bitrate,
1171 .timing_min = {
1172 .sjw = 0x1,
1173 .prop_seg = 0x00,
1174 .phase_seg1 = 0x04,
1175 .phase_seg2 = 0x02,
1176 .prescaler = 0x01
1177 },
1178 .timing_max = {
1179 .sjw = 0x4,
1180 .prop_seg = 0x00,
1181 .phase_seg1 = 0x10,
1182 .phase_seg2 = 0x08,
1183 .prescaler = 0x400
1184 }
1185 };
1186
1187 /* Device Instantiation */
1188 #define CAN_RCAR_INIT(n) \
1189 PINCTRL_DT_INST_DEFINE(n); \
1190 static void can_rcar_##n##_init(const struct device *dev); \
1191 static const struct can_rcar_cfg can_rcar_cfg_##n = { \
1192 .reg_addr = DT_INST_REG_ADDR(n), \
1193 .reg_size = DT_INST_REG_SIZE(n), \
1194 .init_func = can_rcar_##n##_init, \
1195 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1196 .mod_clk.module = \
1197 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
1198 .mod_clk.domain = \
1199 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
1200 .bus_clk.module = \
1201 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
1202 .bus_clk.domain = \
1203 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
1204 .bus_clk.rate = 40000000, \
1205 .bus_speed = DT_INST_PROP(n, bus_speed), \
1206 .sjw = DT_INST_PROP(n, sjw), \
1207 .prop_seg = DT_INST_PROP_OR(n, prop_seg, 0), \
1208 .phase_seg1 = DT_INST_PROP_OR(n, phase_seg1, 0), \
1209 .phase_seg2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
1210 .sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
1211 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1212 .phy = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(n, phys)), \
1213 .max_bitrate = DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(n, 1000000), \
1214 }; \
1215 static struct can_rcar_data can_rcar_data_##n; \
1216 \
1217 CAN_DEVICE_DT_INST_DEFINE(n, can_rcar_init, \
1218 NULL, \
1219 &can_rcar_data_##n, \
1220 &can_rcar_cfg_##n, \
1221 POST_KERNEL, \
1222 CONFIG_CAN_INIT_PRIORITY, \
1223 &can_rcar_driver_api \
1224 ); \
1225 static void can_rcar_##n##_init(const struct device *dev) \
1226 { \
1227 IRQ_CONNECT(DT_INST_IRQN(n), \
1228 0, \
1229 can_rcar_isr, \
1230 DEVICE_DT_INST_GET(n), 0); \
1231 \
1232 irq_enable(DT_INST_IRQN(n)); \
1233 }
1234
1235 DT_INST_FOREACH_STATUS_OKAY(CAN_RCAR_INIT)
1236
