1 /*
2 * Copyright (c) 2019 SEAL AG
3 *
4 * Based on NXP K6x soc.c, which is:
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
6 * Copyright (c) 2016, Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <fsl_common.h>
15 #include <fsl_clock.h>
16
17 #define PERIPH_CLK_PLLFLLSEL (1)
18 #define PERIPH_CLK_OSCERCLK (2)
19 #define PERIPH_CLK_MCGIRCLK (3)
20
21 #define RUNM_RUN (0)
22 #define RUNM_VLPR (2)
23 #define RUNM_HSRUN (3)
24
25 #define CLOCK_NODEID(clk) \
26 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
27
28 #define CLOCK_DIVIDER(clk) \
29 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
30
31 static const osc_config_t osc_config = {
32 .freq = CONFIG_OSC_XTAL0_FREQ,
33 .capLoad = 0,
34
35 #if defined(CONFIG_OSC_EXTERNAL)
36 .workMode = kOSC_ModeExt,
37 #elif defined(CONFIG_OSC_LOW_POWER)
38 .workMode = kOSC_ModeOscLowPower,
39 #elif defined(CONFIG_OSC_HIGH_GAIN)
40 .workMode = kOSC_ModeOscHighGain,
41 #else
42 #error "An oscillator mode must be defined"
43 #endif
44
45 .oscerConfig = {
46 .enableMode = kOSC_ErClkEnable,
47 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
48 FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
49 .erclkDiv = 0U,
50 #endif
51 },
52 };
53
54 static const mcg_pll_config_t pll0_config = {
55 .enableMode = 0U,
56 .prdiv = CONFIG_MCG_PRDIV0,
57 .vdiv = CONFIG_MCG_VDIV0,
58 };
59
60 static const sim_clock_config_t sim_config = {
61 .pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
62 .er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
63 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
64 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
65 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
66 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
67 /* Divide PLL output frequency by 2 for peripherals */
68 .pllFllDiv = (1),
69 .pllFllFrac = (0),
70 };
71
clk_init(void)72 static ALWAYS_INLINE void clk_init(void)
73 {
74 CLOCK_SetSimSafeDivs();
75
76 CLOCK_InitOsc0(&osc_config);
77 CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
78
79 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0_config);
80
81 CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
82 CONFIG_MCG_FCRDIV);
83
84 CLOCK_SetSimConfig(&sim_config);
85
86 #if CONFIG_UART_MCUX_LPUART
87 CLOCK_SetLpuartClock(PERIPH_CLK_PLLFLLSEL);
88 #endif
89
90 #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
91 CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, 120000000UL);
92 #endif
93 }
94
k8x_init(void)95 static int k8x_init(void)
96 {
97 #if !defined(CONFIG_ARM_MPU)
98 uint32_t temp_reg;
99 #endif /* !CONFIG_ARM_MPU */
100
101 /* release I/O power hold to allow normal run state */
102 PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
103
104 #if !defined(CONFIG_ARM_MPU)
105 /*
106 * Disable memory protection and clear slave port errors.
107 * Note that the K8x does not implement the optional ARMv7-M memory
108 * protection unit (MPU), specified by the architecture (PMSAv7), in the
109 * Cortex-M4 core. Instead, the processor includes its own MPU module.
110 */
111 temp_reg = SYSMPU->CESR;
112 temp_reg &= ~SYSMPU_CESR_VLD_MASK;
113 temp_reg |= SYSMPU_CESR_SPERR_MASK;
114 SYSMPU->CESR = temp_reg;
115 #endif /* !CONFIG_ARM_MPU */
116
117 /* Initialize system clocks and PLL */
118 clk_init();
119
120 return 0;
121 }
122
123 #ifdef CONFIG_PLATFORM_SPECIFIC_INIT
124
z_arm_platform_init(void)125 void z_arm_platform_init(void)
126 {
127 SystemInit();
128 }
129
130 #endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
131
132 SYS_INIT(k8x_init, PRE_KERNEL_1, 0);
133
