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Searched refs:MPU_REGION_ENTRY (Results 1 – 21 of 21) sorted by relevance

/Zephyr-Core-3.5.0/boards/arc/nsim/
Darc_mpu_regions.c20 MPU_REGION_ENTRY("COVERAGE",
29 MPU_REGION_ENTRY("ICCM",
36 MPU_REGION_ENTRY("DCCM",
43 MPU_REGION_ENTRY("XCCM",
50 MPU_REGION_ENTRY("YCCM",
61 MPU_REGION_ENTRY("RAM",
66 MPU_REGION_ENTRY("RAM_RX",
71 MPU_REGION_ENTRY("RAM_RW",
80 MPU_REGION_ENTRY("FLASH",
95 MPU_REGION_ENTRY("PERIPHERAL",
/Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32h7/
Dmpu_regions.c11 MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
13 MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
19 MPU_REGION_ENTRY("SYSTEM", 0x1FF00000,
26 MPU_REGION_ENTRY("SRAM3_ETH_BUF",
29 MPU_REGION_ENTRY("SRAM3_ETH_DESC",
33 MPU_REGION_ENTRY("SRAM2_ETH_BUF",
36 MPU_REGION_ENTRY("SRAM2_ETH_DESC",
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/mimx8ml8_m7/
Dmpu_regions.c26 MPU_REGION_ENTRY("MASK", REGION_MASK_BASE_ADDRESS,
34 MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS,
42 MPU_REGION_ENTRY("QSPI", REGION_QSPI_BASE_ADDRESS,
50 MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
58 MPU_REGION_ENTRY("DDR", REGION_DDR_BASE_ADDRESS,
76 MPU_REGION_ENTRY("DDR2", REGION_DDR2_BASE_ADDRESS,
82 MPU_REGION_ENTRY("DDR_NONCACHE", REGION_DDR_NONCACHE_BASE_ADDRESS,
/Zephyr-Core-3.5.0/boards/arc/iotdk/
Darc_mpu_regions.c13 MPU_REGION_ENTRY("ICCM",
18 MPU_REGION_ENTRY("DCCM",
24 MPU_REGION_ENTRY("XCCM",
31 MPU_REGION_ENTRY("YCCM",
37 MPU_REGION_ENTRY("SRAM",
42 MPU_REGION_ENTRY("FLASH_0",
47 MPU_REGION_ENTRY("PERIPHERAL",
/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/k6x/
Dnxp_mpu_regions.c14 MPU_REGION_ENTRY("DEBUGGER_0",
31 MPU_REGION_ENTRY("BACKGROUND_0",
36 MPU_REGION_ENTRY("BACKGROUND_1",
42 MPU_REGION_ENTRY("FLASH_0",
48 MPU_REGION_ENTRY("RAM_U_0",
/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/k8x/
Dnxp_mpu_regions.c11 MPU_REGION_ENTRY("DEBUGGER_0",
28 MPU_REGION_ENTRY("BACKGROUND_0",
33 MPU_REGION_ENTRY("BACKGROUND_1",
39 MPU_REGION_ENTRY("FLASH_0",
45 MPU_REGION_ENTRY("RAM_U_0",
/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ke1xf/
Dnxp_mpu_regions.c11 MPU_REGION_ENTRY("DEBUGGER_0",
28 MPU_REGION_ENTRY("BACKGROUND_0",
33 MPU_REGION_ENTRY("BACKGROUND_1",
39 MPU_REGION_ENTRY("FLASH_0",
45 MPU_REGION_ENTRY("RAM_U_0",
/Zephyr-Core-3.5.0/boards/arc/qemu_arc/
Darc_mpu_regions.c20 MPU_REGION_ENTRY("COVERAGE",
30 MPU_REGION_ENTRY("RAM",
40 MPU_REGION_ENTRY("RAM_RX",
45 MPU_REGION_ENTRY("RAM_RW",
55 MPU_REGION_ENTRY("FLASH",
68 MPU_REGION_ENTRY("PERIPHERAL",
/Zephyr-Core-3.5.0/boards/arc/emsdp/
Darc_mpu_regions.c13 MPU_REGION_ENTRY("ICCM",
18 MPU_REGION_ENTRY("DCCM",
24 MPU_REGION_ENTRY("XCCM",
31 MPU_REGION_ENTRY("YCCM",
37 MPU_REGION_ENTRY("SRAM",
44 MPU_REGION_ENTRY("PERIPHERAL",
/Zephyr-Core-3.5.0/soc/arm/nxp_s32/s32ze/
Dmpu_regions.c14 MPU_REGION_ENTRY("vector",
18 MPU_REGION_ENTRY("SRAM_TEXT",
22 MPU_REGION_ENTRY("SRAM_RODATA",
26 MPU_REGION_ENTRY("SRAM_DATA",
30 MPU_REGION_ENTRY("DEVICE",
/Zephyr-Core-3.5.0/soc/arm/arm/fvp_aemv8r_aarch32/
Darm_mpu_regions.c15 MPU_REGION_ENTRY("vector",
20 MPU_REGION_ENTRY("SRAM_0",
25 MPU_REGION_ENTRY("SRAM_1",
30 MPU_REGION_ENTRY("SRAM_2",
35 MPU_REGION_ENTRY("DEVICE",
/Zephyr-Core-3.5.0/boards/arc/em_starterkit/
Darc_mpu_regions.c18 MPU_REGION_ENTRY("ICCM",
25 MPU_REGION_ENTRY("DCCM",
33 MPU_REGION_ENTRY("XCCM",
40 MPU_REGION_ENTRY("YCCM",
48 MPU_REGION_ENTRY("DDR RAM",
62 MPU_REGION_ENTRY("PERIPHERAL",
/Zephyr-Core-3.5.0/soc/arm64/arm/fvp_aemv8r/
Darm_mpu_regions.c14 MPU_REGION_ENTRY("FLASH_0",
21 MPU_REGION_ENTRY("SRAM_0",
27 MPU_REGION_ENTRY("SRAM_1",
33 MPU_REGION_ENTRY("SRAM_2",
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynqmp/
Darm_mpu_regions.c40 MPU_REGION_ENTRY("FLASH0",
45 MPU_REGION_ENTRY("SRAM_PRIV",
50 MPU_REGION_ENTRY("SRAM",
55 MPU_REGION_ENTRY("REGISTERS",
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/
Dmpu_regions.c14 MPU_REGION_ENTRY("FLASH_0",
18 MPU_REGION_ENTRY("SRAM_0",
28 MPU_REGION_ENTRY("SDRAM0", SDRAM_BASE_ADDR, REGION_IO_ATTR(REGION_512M)),
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/npcx7/
Dmpu_regions.c10 MPU_REGION_ENTRY("FLASH_0_0",
14 MPU_REGION_ENTRY("FLASH_0_1",
18 MPU_REGION_ENTRY("SRAM_0",
/Zephyr-Core-3.5.0/soc/arm/common/cortex_m/
Darm_mpu_regions.c14 MPU_REGION_ENTRY("FLASH_0",
23 MPU_REGION_ENTRY("SRAM_0",
/Zephyr-Core-3.5.0/include/zephyr/arch/arm/mpu/
Darm_mpu.h49 #define MPU_REGION_ENTRY(_name, _base, _size, _attr) \ macro
57 #define MPU_REGION_ENTRY(_name, _base, _attr) \ macro
Dnxp_mpu.h232 #define MPU_REGION_ENTRY(_name, _base, _end, _attr) \ macro
/Zephyr-Core-3.5.0/include/zephyr/arch/arc/v2/mpu/
Darc_mpu.h96 #define MPU_REGION_ENTRY(_name, _base, _size, _attr) \ macro
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/cortex_r/
Darm_mpu.h222 #define MPU_REGION_ENTRY(_name, _base, _limit, _attr) \ macro