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Searched refs:MPU_RASR_XN_Msk (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.5.0/samples/application_development/code_relocation_nocopy/src/
Dmain.c34 if (MPU->RASR & MPU_RASR_XN_Msk) { in disable_mpu_rasr_xn()
35 MPU->RASR ^= MPU_RASR_XN_Msk; in disable_mpu_rasr_xn()
/Zephyr-Core-3.5.0/tests/application_development/code_relocation/src/
Dmain.c34 if (MPU->RASR & MPU_RASR_XN_Msk) { in disable_mpu_rasr_xn()
35 MPU->RASR ^= MPU_RASR_XN_Msk; in disable_mpu_rasr_xn()
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynqmp/
Darm_mpu_regions.c15 | MPU_RASR_XN_Msk) \
/Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32h7/
Dmpu_regions.c22 MPU_RASR_XN_Msk | P_RW_U_NA_Msk) }),
/Zephyr-Core-3.5.0/include/zephyr/arch/arm/mpu/
Darm_mpu_v7m.h46 #define NOT_EXEC MPU_RASR_XN_Msk
127 IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \
132 MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_a_r/
Dmpu.h18 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) macro