MIO_PIN_L0_SEL (reference) in projects: Zephyr-Core-3.5.0

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/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
D	pinctrl_soc.h	`41 #define MIO_PIN_L0_SEL(val) FIELD_PREP(MIO_PIN_L0_SEL_MASK, val) macro 50 (MIO_PIN_L3_SEL(l3) \| MIO_PIN_L2_SEL(l2) \| MIO_PIN_L1_SEL(l1) \| MIO_PIN_L0_SEL(l0))`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
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