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Searched refs:MASK (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.5.0/drivers/dma/
Ddma_dw_common.h17 #define MASK(b_hi, b_lo) \ macro
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
137 #define DW_CTLL_SRC_WIDTH_MASK MASK(6, 4)
139 #define DW_CTLL_DST_WIDTH_MASK MASK(3, 1)
146 #define DW_CTLH_BLOCK_TS_MASK MASK(16, 0)
/Zephyr-Core-3.5.0/samples/boards/up_squared/gpio_counter/src/
Dmain.c82 #define MASK (BIT(NUM_PINS) - 1) macro
168 val = counter & MASK; in main()
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_mcux_lpc.c160 gpio_base->MASK[port] = ~mask; in gpio_mcux_lpc_port_set_masked_raw()
163 gpio_base->MASK[port] = 0U; in gpio_mcux_lpc_port_set_masked_raw()
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_gicv3_priv.h276 #define MASK(__basename) (__basename##_MASK << __basename##_SHIFT) macro
Dintc_gicv3_its.c86 reg &= ~MASK(GITS_CTLR_ENABLED); in its_force_quiescent()
120 reg &= ~MASK(GITS_BASER_PAGE_SIZE); in its_probe_baser_page_size()
/Zephyr-Core-3.5.0/drivers/dai/intel/ssp/
Dssp.h23 (((x) & MASK(b_hi, b_lo)) >> (b_lo))
/Zephyr-Core-3.5.0/doc/build/kconfig/
Dtips.rst928 by the user. For example, a value ``MASK`` that's hardcoded to 0xFF on some
933 config MASK
943 config MASK
949 indicate that ``MASK`` is configurable. When ``MASK`` is configurable, it will