1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and 2 * temperature sensor driver 3 */ 4 5 /* 6 * Copyright (c) 2017 Linaro Limited 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_SENSOR_LSM6DSL_LSM6DSL_H_ 12 #define ZEPHYR_DRIVERS_SENSOR_LSM6DSL_LSM6DSL_H_ 13 14 #include <zephyr/drivers/sensor.h> 15 #include <zephyr/types.h> 16 #include <zephyr/drivers/gpio.h> 17 #include <zephyr/kernel.h> 18 #include <zephyr/sys/util.h> 19 20 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 21 #include <zephyr/drivers/spi.h> 22 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 23 24 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 25 #include <zephyr/drivers/i2c.h> 26 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 27 28 #define LSM6DSL_REG_FUNC_CFG_ACCESS 0x01 29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7) 30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7 31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5) 32 #define LSM6DSL_SHIFT_FUNC_CFG_EN_B 5 33 34 #define LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME 0x04 35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \ 36 BIT(1) | BIT(0)) 37 #define LSM6DSL_SHIFT_SENSOR_SYNC_TIME_FRAME_TPH 0 38 39 #define LSM6DSL_REG_SENSOR_SYNC_RES_RATIO 0x05 40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0)) 41 #define LSM6DSL_SHIFT_SENSOR_SYNC_RES_RATIO 0 42 43 #define LSM6DSL_REG_FIFO_CTRL1 0x06 44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \ 45 BIT(5) | BIT(4) | \ 46 BIT(3) | BIT(2) | \ 47 BIT(1) | BIT(0)) 48 #define LSM6DSL_SHIFT_FIFO_CTRL1_FTH 0 49 50 #define LSM6DSL_REG_FIFO_CTRL2 0x07 51 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7) 52 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_EN 7 53 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY BIT(6) 54 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY 6 55 #define LSM6DSL_MASK_FIFO_CTRL2_FIFO_TEMP_EN BIT(3) 56 #define LSM6DSL_SHIFT_FIFO_CTRL2_FIFO_TEMP_EN 3 57 #define LSM6DSL_MASK_FIFO_CTRL2_FTH (BIT(2) | BIT(1) | \ 58 BIT(0)) 59 #define LSM6DSL_SHIFT_FIFO_CTRL2_FTH 0 60 61 #define LSM6DSL_REG_FIFO_CTRL3 0x08 62 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_GYRO (BIT(5) | BIT(4) | \ 63 BIT(3)) 64 #define LSM6DSL_SHIFT_FIFO_CTRL3_DEC_FIFO_GYRO 3 65 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_XL (BIT(2) | BIT(1) | \ 66 BIT(0)) 67 #define LSM6DSL_SHIFT_FIFO_CTRL3_DEC_FIFO_XL 0 68 69 #define LSM6DSL_REG_FIFO_CTRL4 0x09 70 #define LSM6DSL_MASK_FIFO_CTRL4_STOP_ON_FTH BIT(7) 71 #define LSM6DSL_SHIFT_FIFO_CTRL4_STOP_ON_FTH 7 72 #define LSM6DSL_MASK_FIFO_CTRL4_ONLY_HIGH_DATA BIT(6) 73 #define LSM6DSL_SHIFT_FIFO_CTRL4_ONLY_HIGH_DATA 6 74 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS4_FIFO (BIT(5) | BIT(4) | \ 75 BIT(3)) 76 #define LSM6DSL_SHIFT_FIFO_CTRL4_DEC_DS4_FIFO 3 77 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS3_FIFO (BIT(2) | BIT(1) | \ 78 BIT(0)) 79 #define LSM6DSL_SHIFT_FIFO_CTRL4_DEC_DS3_FIFO 0 80 81 #define LSM6DSL_REG_FIFO_CTRL5 0x0A 82 #define LSM6DSL_MASK_FIFO_CTRL5_ODR_FIFO (BIT(6) | BIT(5) | \ 83 BIT(4) | BIT(3)) 84 #define LSM6DSL_SHIFT_FIFO_CTRL5_ODR_FIFO 3 85 #define LSM6DSL_MASK_FIFO_CTRL5_FIFO_MODE (BIT(2) | BIT(1) | \ 86 BIT(0)) 87 #define LSM6DSL_SHIFT_FIFO_CTRL5_FIFO_MODE 0 88 89 #define LSM6DSL_REG_DRDY_PULSE_CFG_G 0x0B 90 #define LSM6DSL_MASK_DRDY_PULSE_CFG_G_DRDY_PULSED BIT(7) 91 #define LSM6DSL_SHIFT_DRDY_PULSE_CFG_G_DRDY_PULSED 7 92 #define LSM6DSL_MASK_DRDY_PULSE_CFG_G_INT2_WRIST_TILT BIT(0) 93 #define LSM6DSL_SHIFT_DRDY_PULSE_CFG_G_INT2_WRIST_TILT 0 94 95 #define LSM6DSL_REG_INT1_CTRL 0x0D 96 #define LSM6DSL_MASK_INT1_CTRL_STEP_DETECTOR BIT(7) 97 #define LSM6DSL_SHIFT_INT1_CTRL_STEP_DETECTOR 7 98 #define LSM6DSL_MASK_INT1_CTRL_SIGN_MOT BIT(6) 99 #define LSM6DSL_SHIFT_INT1_CTRL_SIGN_MOT 6 100 #define LSM6DSL_MASK_INT1_CTRL_FULL_FLAG BIT(5) 101 #define LSM6DSL_SHIFT_INT1_CTRL_FULL_FLAG 5 102 #define LSM6DSL_MASK_INT1_CTRL_FIFO_OVR BIT(4) 103 #define LSM6DSL_SHIFT_INT1_CTRL_FIFO_OVR 4 104 #define LSM6DSL_MASK_INT1_FTH BIT(3) 105 #define LSM6DSL_SHIFT_INT1_FTH 3 106 #define LSM6DSL_MASK_INT1_CTRL_BOOT BIT(2) 107 #define LSM6DSL_SHIFT_INT1_CTRL_BOOT 2 108 #define LSM6DSL_MASK_INT1_CTRL_DRDY_G BIT(1) 109 #define LSM6DSL_SHIFT_INT1_CTRL_DRDY_G 1 110 #define LSM6DSL_MASK_INT1_CTRL_DRDY_XL BIT(0) 111 #define LSM6DSL_SHIFT_INT1_CTRL_DRDY_XL 0 112 113 #define LSM6DSL_REG_INT2_CTRL 0x0E 114 #define LSM6DSL_MASK_INT2_CTRL_STEP_DELTA BIT(7) 115 #define LSM6DSL_SHIFT_INT2_CTRL_STEP_DELTA 7 116 #define LSM6DSL_MASK_INT2_CTRL_STEP_COUNT_OV BIT(6) 117 #define LSM6DSL_SHIFT_INT2_CTRL_STEP_COUNT_OV 6 118 #define LSM6DSL_MASK_INT2_CTRL_FULL_FLAG BIT(5) 119 #define LSM6DSL_SHIFT_INT2_CTRL_FULL_FLAG 5 120 #define LSM6DSL_MASK_INT2_CTRL_FIFO_OVR BIT(4) 121 #define LSM6DSL_SHIFT_INT2_CTRL_FIFO_OVR 4 122 #define LSM6DSL_MASK_INT2_FTH BIT(3) 123 #define LSM6DSL_SHIFT_INT2_FTH 3 124 #define LSM6DSL_MASK_INT2_DRDY_TEMP BIT(2) 125 #define LSM6DSL_SHIFT_INT2_DRDY_TEMP 2 126 #define LSM6DSL_MASK_INT2_CTRL_DRDY_G BIT(1) 127 #define LSM6DSL_SHIFT_INT2_CTRL_DRDY_G 1 128 #define LSM6DSL_MASK_INT2_CTRL_DRDY_XL BIT(0) 129 #define LSM6DSL_SHIFT_INT2_CTRL_DRDY_XL 0 130 131 #define LSM6DSL_REG_WHO_AM_I 0x0F 132 #define LSM6DSL_VAL_WHO_AM_I 0x6A 133 134 #define LSM6DSL_REG_CTRL1_XL 0x10 135 #define LSM6DSL_MASK_CTRL1_XL_ODR_XL (BIT(7) | BIT(6) | \ 136 BIT(5) | BIT(4)) 137 #define LSM6DSL_SHIFT_CTRL1_XL_ODR_XL 4 138 #define LSM6DSL_MASK_CTRL1_XL_FS_XL (BIT(3) | BIT(2)) 139 #define LSM6DSL_SHIFT_CTRL1_XL_FS_XL 2 140 #define LSM6DSL_MASK_CTRL1_XL_LPF1_BW_SEL BIT(1) 141 #define LSM6DSL_SHIFT_CTRL1_XL_LPF1_BW_SEL 1 142 143 #define LSM6DSL_REG_CTRL2_G 0x11 144 #define LSM6DSL_MASK_CTRL2_G_ODR_G (BIT(7) | BIT(6) | \ 145 BIT(5) | BIT(4)) 146 #define LSM6DSL_SHIFT_CTRL2_G_ODR_G 4 147 #define LSM6DSL_MASK_CTRL2_G_FS_G (BIT(3) | BIT(2)) 148 #define LSM6DSL_SHIFT_CTRL2_G_FS_G 2 149 #define LSM6DSL_MASK_CTRL2_FS125 BIT(1) 150 #define LSM6DSL_SHIFT_CTRL2_FS125 1 151 152 #define LSM6DSL_REG_CTRL3_C 0x12 153 #define LSM6DSL_MASK_CTRL3_C_BOOT BIT(7) 154 #define LSM6DSL_SHIFT_CTRL3_C_BOOT 7 155 #define LSM6DSL_MASK_CTRL3_C_BDU BIT(6) 156 #define LSM6DSL_SHIFT_CTRL3_C_BDU 6 157 #define LSM6DSL_MASK_CTRL3_C_H_LACTIVE BIT(5) 158 #define LSM6DSL_SHIFT_CTRL3_C_H_LACTIVE 5 159 #define LSM6DSL_MASK_CTRL3_C_PP_OD BIT(4) 160 #define LSM6DSL_SHIFT_CTRL3_C_PP_OD 4 161 #define LSM6DSL_MASK_CTRL3_C_SIM BIT(3) 162 #define LSM6DSL_SHIFT_CTRL3_C_SIM 3 163 #define LSM6DSL_MASK_CTRL3_C_IF_INC BIT(2) 164 #define LSM6DSL_SHIFT_CTRL3_C_IF_INC 2 165 #define LSM6DSL_MASK_CTRL3_C_BLE BIT(1) 166 #define LSM6DSL_SHIFT_CTRL3_C_BLE 1 167 #define LSM6DSL_MASK_CTRL3_C_SW_RESET BIT(0) 168 #define LSM6DSL_SHIFT_CTRL3_C_SW_RESET 0 169 170 #define LSM6DSL_REG_CTRL4_C 0x13 171 #define LSM6DSL_MASK_CTRL4_C_DEN_XL_EN BIT(7) 172 #define LSM6DSL_SHIFT_CTRL4_C_DEN_XL_EN 7 173 #define LSM6DSL_MASK_CTRL4_C_SLEEP BIT(6) 174 #define LSM6DSL_SHIFT_CTRL4_C_SLEEP 6 175 #define LSM6DSL_MASK_CTRL4_C_INT2_ON_INT1 BIT(5) 176 #define LSM6DSL_SHIFT_CTRL4_C_INT2_ON_INT1 5 177 #define LSM6DSL_MASK_CTRL4_C_DEN_DRDY_INT1 BIT(4) 178 #define LSM6DSL_SHIFT_CTRL4_C_DEN_DRDY_INT1 4 179 #define LSM6DSL_MASK_CTRL4_C_DRDY_MASK BIT(3) 180 #define LSM6DSL_SHIFT_CTRL4_C_DRDY_MASK 3 181 #define LSM6DSL_MASK_CTRL4_C_I2C_DISABLE BIT(2) 182 #define LSM6DSL_SHIFT_CTRL4_C_I2C_DISABLE 2 183 #define LSM6DSL_MASK_CTRL4_C_LPF1_SEL_G BIT(1) 184 #define LSM6DSL_SHIFT_CTRL4_C_LPF1_SEL_G 1 185 186 #define LSM6DSL_REG_CTRL5_C 0x14 187 #define LSM6DSL_MASK_CTRL5_C_ROUNDING (BIT(7) | BIT(6) | \ 188 BIT(5)) 189 #define LSM6DSL_SHIFT_CTRL5_C_ROUNDING 5 190 #define LSM6DSL_MASK_CTRL5_C_DEN_LH BIT(4) 191 #define LSM6DSL_SHIFT_CTRL5_C_DEN_LH 4 192 #define LSM6DSL_MASK_CTRL5_C_ST_G (BIT(3) | BIT(2)) 193 #define LSM6DSL_SHIFT_CTRL5_C_ST_G 2 194 #define LSM6DSL_MASK_CTRL5_C_ST_XL (BIT(1) | BIT(0)) 195 #define LSM6DSL_SHIFT_CTRL5_C_ST_XL 0 196 197 #define LSM6DSL_REG_CTRL6_C 0x15 198 #define LSM6DSL_MASK_CTRL6_C_TRIG_EN BIT(7) 199 #define LSM6DSL_SHIFT_CTRL6_C_TRIG_EN 7 200 #define LSM6DSL_MASK_CTRL6_C_LVL_EN BIT(6) 201 #define LSM6DSL_SHIFT_CTRL6_C_LVL_EN 6 202 #define LSM6DSL_MASK_CTRL6_C_LVL2_EN BIT(5) 203 #define LSM6DSL_SHIFT_CTRL6_C_LVL2_EN 5 204 #define LSM6DSL_MASK_CTRL6_C_XL_HM_MODE BIT(4) 205 #define LSM6DSL_SHIFT_CTRL6_C_XL_HM_MODE 4 206 #define LSM6DSL_MASK_CTRL6_C_USR_OFF_W BIT(3) 207 #define LSM6DSL_SHIFT_CTRL6_C_USR_OFF_W 3 208 #define LSM6DSL_MASK_CTRL6_C_FTYPE (BIT(0) | BIT(1)) 209 #define LSM6DSL_SHIFT_CTRL6_C_FTYPE 0 210 211 #define LSM6DSL_REG_CTRL7_G 0x16 212 #define LSM6DSL_MASK_CTRL7_G_HM_MODE BIT(7) 213 #define LSM6DSL_SHIFT_CTRL7_G_HM_MODE 7 214 #define LSM6DSL_MASK_CTRL7_HP_EN_G BIT(6) 215 #define LSM6DSL_SHIFT_CTRL7_HP_EN_G 6 216 #define LSM6DSL_MASK_CTRL7_HPM_G (BIT(5) | BIT(4)) 217 #define LSM6DSL_SHIFT_CTRL7_HPM_G 4 218 #define LSM6DSL_MASK_CTRL7_ROUNDING_STATUS BIT(2) 219 #define LSM6DSL_SHIFT_CTRL7_ROUNDING_STATUS 2 220 221 #define LSM6DSL_REG_CTRL8_XL 0x17 222 #define LSM6DSL_MASK_CTRL8_LPF2_XL_EN BIT(7) 223 #define LSM6DSL_SHIFT_CTRL8_LPF2_XL_EN 7 224 #define LSM6DSL_MASK_CTRL8_HPCF_XL (BIT(6) | BIT(5)) 225 #define LSM6DSL_SHIFT_CTRL8_HPCF_XL 5 226 #define LSM6DSL_MASK_CTRL8_HP_REF_MODE BIT(4) 227 #define LSM6DSL_SHIFT_CTRL8_HP_REF_MODE 4 228 #define LSM6DSL_MASK_CTRL8_INPUT_COMPOSITE BIT(3) 229 #define LSM6DSL_SHIFT_CTRL8_INPUT_COMPOSITE 3 230 #define LSM6DSL_MASK_CTRL8_HP_SLOPE_XL_EN BIT(2) 231 #define LSM6DSL_SHIFT_CTRL8_HP_SLOPE_XL_EN 2 232 #define LSM6DSL_MASK_CTRL8_LOW_PASS_ON_6D BIT(0) 233 #define LSM6DSL_SHIFT_CTRL8_LOW_PASS_ON_6D 0 234 235 #define LSM6DSL_REG_CTRL9_XL 0x18 236 #define LSM6DSL_MASK_CTRL9_XL_DEN_X BIT(7) 237 #define LSM6DSL_SHIFT_CTRL9_XL_DEN_X 7 238 #define LSM6DSL_MASK_CTRL9_XL_DEN_Y BIT(6) 239 #define LSM6DSL_SHIFT_CTRL9_XL_DEN_Y 6 240 #define LSM6DSL_MASK_CTRL9_XL_DEN_Z BIT(5) 241 #define LSM6DSL_SHIFT_CTRL9_XL_DEN_Z 5 242 #define LSM6DSL_MASK_CTRL9_XL_DEN_G BIT(4) 243 #define LSM6DSL_SHIFT_CTRL9_XL_DEN_G 4 244 #define LSM6DSL_MASK_CTRL9_XL_SOFT_EN BIT(2) 245 #define LSM6DSL_SHIFT_CTRL9_XL_SOFT_EN 2 246 247 #define LSM6DSL_REG_CTRL10_C 0x19 248 #define LSM6DSL_MASK_CTRL10_C_WRIST_TILT_EN BIT(7) 249 #define LSM6DSL_SHIFT_CTRL10_C_WRIST_TILT_EN 7 250 #define LSM6DSL_MASK_CTRL10_C_TIMER_EN BIT(5) 251 #define LSM6DSL_SHIFT_CTRL10_C_TIMER_EN 5 252 #define LSM6DSL_MASK_CTRL10_C_PEDO_EN BIT(4) 253 #define LSM6DSL_SHIFT_CTRL10_C_PEDO_EN 4 254 #define LSM6DSL_MASK_CTRL10_C_TILT_EN BIT(3) 255 #define LSM6DSL_SHIFT_CTRL10_C_TILT_EN 3 256 #define LSM6DSL_MASK_CTRL10_C_FUNC_EN BIT(2) 257 #define LSM6DSL_SHIFT_CTRL10_C_FUNC_EN 2 258 #define LSM6DSL_MASK_CTRL10_C_PEDO_RST_STEP BIT(1) 259 #define LSM6DSL_SHIFT_CTRL10_C_PEDO_RST_STEP 1 260 #define LSM6DSL_MASK_CTRL10_C_SIGN_MOTION_EN BIT(0) 261 #define LSM6DSL_SHIFT_CTRL10_C_SIGN_MOTION_EN 0 262 263 #define LSM6DSL_REG_MASTER_CONFIG 0x1A 264 #define LSM6DSL_MASK_MASTER_CONFIG_DRDY_ON_INT1 BIT(7) 265 #define LSM6DSL_SHIFT_MASTER_CONFIG_DRDY_ON_INT1 7 266 #define LSM6DSL_MASK_MASTER_CONFIG_DATA_VALID_SEL_FIFO BIT(6) 267 #define LSM6DSL_SHIFT_MASTER_CONFIG_DATA_VALID_SEL_FIFO 6 268 #define LSM6DSL_MASK_MASTER_CONFIG_START_CONFIG BIT(4) 269 #define LSM6DSL_SHIFT_MASTER_CONFIG_START_CONFIG 4 270 #define LSM6DSL_MASK_MASTER_CONFIG_PULL_UP_EN BIT(3) 271 #define LSM6DSL_SHIFT_MASTER_CONFIG_PULL_UP_EN 3 272 #define LSM6DSL_MASK_MASTER_CONFIG_PASS_THROUGH_MODE BIT(2) 273 #define LSM6DSL_SHIFT_MASTER_CONFIG_PASS_THROUGH_MODE 2 274 #define LSM6DSL_MASK_MASTER_CONFIG_IRON_EN BIT(1) 275 #define LSM6DSL_SHIFT_MASTER_CONFIG_IRON_EN 1 276 #define LSM6DSL_MASK_MASTER_CONFIG_MASTER_ON BIT(0) 277 #define LSM6DSL_SHIFT_MASTER_CONFIG_MASTER_ON 0 278 279 #define LSM6DSL_REG_WAKE_UP_SRC 0x1B 280 #define LSM6DSL_MASK_WAKE_UP_SRC_FF_IA BIT(5) 281 #define LSM6DSL_SHIFT_WAKE_UP_SRC_FF_IA 5 282 #define LSM6DSL_MASK_WAKE_UP_SRC_SLEEP_STATE_IA BIT(4) 283 #define LSM6DSL_SHIFT_WAKE_UP_SRC_SLEEP_STATE_IA 4 284 #define LSM6DSL_MASK_WAKE_UP_SRC_WU_IA BIT(3) 285 #define LSM6DSL_SHIFT_WAKE_UP_SRC_WU_IA 3 286 #define LSM6DSL_MASK_WAKE_UP_SRC_X_WU BIT(2) 287 #define LSM6DSL_SHIFT_WAKE_UP_SRC_X_WU 2 288 #define LSM6DSL_MASK_WAKE_UP_SRC_Y_WU BIT(1) 289 #define LSM6DSL_SHIFT_WAKE_UP_SRC_Y_WU 1 290 #define LSM6DSL_MASK_WAKE_UP_SRC_Z_WU BIT(0) 291 #define LSM6DSL_SHIFT_WAKE_UP_SRC_Z_WU 0 292 293 #define LSM6DSL_REG_TAP_SRC 0x1C 294 #define LSM6DSL_MASK_TAP_SRC_TAP_IA BIT(6) 295 #define LSM6DSL_SHIFT_TAP_SRC_TAP_IA 6 296 #define LSM6DSL_MASK_TAP_SRC_SINGLE_TAP BIT(5) 297 #define LSM6DSL_SHIFT_TAP_SRC_SINGLE_TAP 5 298 #define LSM6DSL_MASK_TAP_SRC_DOUBLE_TAP BIT(4) 299 #define LSM6DSL_SHIFT_TAP_SRC_DOUBLE_TAP 4 300 #define LSM6DSL_MASK_TAP_SRC_TAP_SIGN BIT(3) 301 #define LSM6DSL_SHIFT_TAP_SRC_TAP_SIGN 3 302 #define LSM6DSL_MASK_TAP_SRC_X_TAP BIT(2) 303 #define LSM6DSL_SHIFT_TAP_SRC_X_TAP 2 304 #define LSM6DSL_MASK_TAP_SRC_Y_TAP BIT(1) 305 #define LSM6DSL_SHIFT_TAP_SRC_Y_TAP 1 306 #define LSM6DSL_MASK_TAP_SRC_Z_TAP BIT(0) 307 #define LSM6DSL_SHIFT_TAP_SRC_Z_TAP 0 308 309 #define LSM6DSL_REG_D6D_SRC 0x1D 310 #define LSM6DSL_MASK_D6D_SRC_DEN_DRDY BIT(7) 311 #define LSM6DSL_SHIFT_D6D_SRC_DEN_DRDY 7 312 #define LSM6DSL_MASK_D6D_SRC_D6D_IA BIT(6) 313 #define LSM6DSL_SHIFT_D6D_SRC_D6D_IA 6 314 #define LSM6DSL_MASK_D6D_SRC_ZH BIT(5) 315 #define LSM6DSL_SHIFT_D6D_SRC_ZH 5 316 #define LSM6DSL_MASK_D6D_SRC_ZL BIT(4) 317 #define LSM6DSL_SHIFT_D6D_SRC_ZL 4 318 #define LSM6DSL_MASK_D6D_SRC_YH BIT(3) 319 #define LSM6DSL_SHIFT_D6D_SRC_YH 3 320 #define LSM6DSL_MASK_D6D_SRC_YL BIT(2) 321 #define LSM6DSL_SHIFT_D6D_SRC_YL 2 322 #define LSM6DSL_MASK_D6D_SRC_XH BIT(1) 323 #define LSM6DSL_SHIFT_D6D_SRC_XH 1 324 #define LSM6DSL_MASK_D6D_SRC_XL BIT(0) 325 #define LSM6DSL_SHIFT_D6D_SRC_XL 0 326 327 #define LSM6DSL_REG_STATUS_REG 0x1E 328 #define LSM6DSL_MASK_STATUS_REG_TDA BIT(2) 329 #define LSM6DSL_SHIFT_STATUS_REG_TDA 2 330 #define LSM6DSL_MASK_STATUS_REG_GDA BIT(1) 331 #define LSM6DSL_SHIFT_STATUS_REG_GDA 1 332 #define LSM6DSL_MASK_STATUS_REG_XLDA BIT(0) 333 #define LSM6DSL_SHIFT_STATUS_REG_XLDA 0 334 335 #define LSM6DSL_REG_OUT_TEMP_L 0x20 336 #define LSM6DSL_REG_OUT_TEMP_H 0x21 337 #define LSM6DSL_REG_OUTX_L_G 0x22 338 #define LSM6DSL_REG_OUTX_H_G 0x23 339 #define LSM6DSL_REG_OUTY_L_G 0x24 340 #define LSM6DSL_REG_OUTY_H_G 0x25 341 #define LSM6DSL_REG_OUTZ_L_G 0x26 342 #define LSM6DSL_REG_OUTZ_H_G 0x27 343 #define LSM6DSL_REG_OUTX_L_XL 0x28 344 #define LSM6DSL_REG_OUTX_H_XL 0x29 345 #define LSM6DSL_REG_OUTY_L_XL 0x2A 346 #define LSM6DSL_REG_OUTY_H_XL 0x2B 347 #define LSM6DSL_REG_OUTZ_L_XL 0x2C 348 #define LSM6DSL_REG_OUTZ_H_XL 0x2D 349 #define LSM6DSL_REG_SENSORHUB1 0x2E 350 #define LSM6DSL_REG_SENSORHUB2 0x2F 351 #define LSM6DSL_REG_SENSORHUB3 0x30 352 #define LSM6DSL_REG_SENSORHUB4 0x31 353 #define LSM6DSL_REG_SENSORHUB5 0x32 354 #define LSM6DSL_REG_SENSORHUB6 0x33 355 #define LSM6DSL_REG_SENSORHUB7 0x34 356 #define LSM6DSL_REG_SENSORHUB8 0x35 357 #define LSM6DSL_REG_SENSORHUB9 0x36 358 #define LSM6DSL_REG_SENSORHUB10 0x37 359 #define LSM6DSL_REG_SENSORHUB11 0x38 360 #define LSM6DSL_REG_SENSORHUB12 0x39 361 #define LSM6DSL_REG_FIFO_STATUS1 0x3A 362 363 #define LSM6DSL_REG_FIFO_STATUS2 0x3B 364 #define LSM6DSL_MASK_FIFO_STATUS2_WATERM BIT(7) 365 #define LSM6DSL_SHIFT_FIFO_STATUS2_WATERM 7 366 #define LSM6DSL_MASK_FIFO_STATUS2_OVER_RUN BIT(6) 367 #define LSM6DSL_SHIFT_FIFO_STATUS2_OVER_RUN 6 368 #define LSM6DSL_MASK_FIFO_STATUS2_FIFO_FULL_SMART BIT(5) 369 #define LSM6DSL_SHIFT_FIFO_STATUS2_FIFO_FULL_SMART 5 370 #define LSM6DSL_MASK_FIFO_STATUS2_FIFO_EMPTY BIT(4) 371 #define LSM6DSL_SHIFT_FIFO_STATUS2_FIFO_EMPTY 4 372 #define LSM6DSL_MASK_FIFO_STATUS2_DIFF_FIFO (BIT(2) | BIT(1) | \ 373 BIT(0)) 374 #define LSM6DSL_SHIFT_FIFO_STATUS2_DIFF_FIFO 0 375 376 #define LSM6DSL_REG_FIFO_STATUS3 0x3C 377 #define LSM6DSL_MASK_FIFO_STATUS3_FIFO_PATTERN 0xFF 378 #define LSM6DSL_SHIFT_FIFO_STATUS3_FIFO_PATTERN 0 379 380 #define LSM6DSL_REG_FIFO_STATUS4 0x3D 381 #define LSM6DSL_MASK_FIFO_STATUS4_FIFO_PATTERN (BIT(1) | BIT(0)) 382 #define LSM6DSL_SHIFT_FIFO_STATUS4_FIFO_PATTERN 0 383 384 #define LSM6DSL_REG_FIFO_DATA_OUT_L 0x3E 385 #define LSM6DSL_REG_FIFO_DATA_OUT_H 0x3F 386 #define LSM6DSL_REG_TIMESTAMP0 0x40 387 #define LSM6DSL_REG_TIMESTAMP1 0x41 388 #define LSM6DSL_REG_TIMESTAMP2 0x42 389 #define LSM6DSL_REG_STEP_TIMESTAMP_L 0x49 390 #define LSM6DSL_REG_STEP_TIMESTAMP_H 0x4A 391 #define LSM6DSL_REG_STEP_COUNTER_L 0x4B 392 #define LSM6DSL_REG_STEP_COUNTER_H 0x4C 393 #define LSM6DSL_REG_SENSORHUB13 0x4D 394 #define LSM6DSL_REG_SENSORHUB14 0x4E 395 #define LSM6DSL_REG_SENSORHUB15 0x4F 396 #define LSM6DSL_REG_SENSORHUB16 0x50 397 #define LSM6DSL_REG_SENSORHUB17 0x51 398 #define LSM6DSL_REG_SENSORHUB18 0x52 399 400 #define LSM6DSL_REG_FUNC_SRC1 0x53 401 #define LSM6DSL_MASK_FUNC_SRC1_STEP_COUNT_DELTA_IA BIT(7) 402 #define LSM6DSL_SHIFT_FUNC_SRC1_STEP_COUNT_DELTA_IA 7 403 #define LSM6DSL_MASK_FUNC_SRC1_SIGN_MOTION_IA BIT(6) 404 #define LSM6DSL_SHIFT_FUNC_SRC1_SIGN_MOTION_IA 6 405 #define LSM6DSL_MASK_FUNC_SRC1_TILT_IA BIT(5) 406 #define LSM6DSL_SHIFT_FUNC_SRC1_TILT_IA 5 407 #define LSM6DSL_MASK_FUNC_SRC1_STEP_DETECTED BIT(4) 408 #define LSM6DSL_SHIFT_FUNC_SRC1_STEP_DETECTED 4 409 #define LSM6DSL_MASK_FUNC_SRC1_STEP_OVERFLOW BIT(3) 410 #define LSM6DSL_SHIFT_FUNC_SRC1_STEP_OVERFLOW 3 411 #define LSM6DSL_MASK_FUNC_SRC1_HI_FAIL BIT(2) 412 #define LSM6DSL_SHIFT_FUNC_SRC1_HI_FAIL 2 413 #define LSM6DSL_MASK_FUNC_SRC1_SI_SEND_OP BIT(1) 414 #define LSM6DSL_SHIFT_FUNC_SRC1_SI_SEND_OP 1 415 #define LSM6DSL_MASK_FUNC_SRC1_SENSORHUB_END_OP BIT(0) 416 #define LSM6DSL_SHIFT_FUNC_SRC1_SENSORHUB_END_OP 0 417 418 #define LSM6DSL_REG_FUNC_SRC2 0x54 419 #define LSM6DSL_MASK_FUNC_SRC2_SLAVE3_NACK BIT(6) 420 #define LSM6DSL_SHIFT_FUNC_SRC2_SLAVE3_NACK 6 421 #define LSM6DSL_MASK_FUNC_SRC2_SLAVE2_NACK BIT(5) 422 #define LSM6DSL_SHIFT_FUNC_SRC2_SLAVE2_NACK 5 423 #define LSM6DSL_MASK_FUNC_SRC2_SLAVE1_NACK BIT(4) 424 #define LSM6DSL_SHIFT_FUNC_SRC2_SLAVE1_NACK 4 425 #define LSM6DSL_MASK_FUNC_SRC2_SLAVE0_NACK BIT(3) 426 #define LSM6DSL_SHIFT_FUNC_SRC2_SLAVE0_NACK 3 427 #define LSM6DSL_MASK_FUNC_SRC2_WRIST_TILT_IA BIT(0) 428 #define LSM6DSL_SHIFT_FUNC_SRC2_WRIST_TILT_IA 0 429 430 #define LSM6DSL_REG_WRIST_TILT_IA 0x55 431 #define LSM6DSL_MASK_WRIST_TILT_IA_XPOS BIT(7) 432 #define LSM6DSL_SHIFT_WRIST_TILT_IA_XPOS 7 433 #define LSM6DSL_MASK_WRIST_TILT_IA_XNEG BIT(6) 434 #define LSM6DSL_SHIFT_WRIST_TILT_IA_XNEG 6 435 #define LSM6DSL_MASK_WRIST_TILT_IA_YPOS BIT(5) 436 #define LSM6DSL_SHIFT_WRIST_TILT_IA_YPOS 5 437 #define LSM6DSL_MASK_WRIST_TILT_IA_YNEG BIT(4) 438 #define LSM6DSL_SHIFT_WRIST_TILT_IA_YNEG 4 439 #define LSM6DSL_MASK_WRIST_TILT_IA_ZPOS BIT(3) 440 #define LSM6DSL_SHIFT_WRIST_TILT_IA_ZPOS 3 441 #define LSM6DSL_MASK_WRIST_TILT_IA_ZNEG BIT(2) 442 #define LSM6DSL_SHIFT_WRIST_TILT_IA_ZNEG 2 443 444 #define LSM6DSL_REG_TAP_CFG 0x58 445 #define LSM6DSL_MASK_TAP_CFG_INTERRPUTS_ENABLE BIT(7) 446 #define LSM6DSL_SHIFT_TAP_CFG_INTERRPUTS_ENABLE 7 447 #define LSM6DSL_MASK_TAP_CFG_INACT_EN (BIT(6) | BIT(5)) 448 #define LSM6DSL_SHIFT_TAP_CFG_INACT_EN 5 449 #define LSM6DSL_MASK_TAP_CFG_SLOPE_FDS BIT(4) 450 #define LSM6DSL_SHIFT_TAP_CFG_SLOPE_FDS 4 451 #define LSM6DSL_MASK_TAP_CFG_X_EN BIT(3) 452 #define LSM6DSL_SHIFT_TAP_CFG_X_EN 3 453 #define LSM6DSL_MASK_TAP_CFG_Y_EN BIT(2) 454 #define LSM6DSL_SHIFT_TAP_CFG_Y_EN 2 455 #define LSM6DSL_MASK_TAP_CFG_Z_EN BIT(1) 456 #define LSM6DSL_SHIFT_TAP_CFG_Z_EN 1 457 #define LSM6DSL_MASK_TAP_CFG_LIR BIT(0) 458 #define LSM6DSL_SHIFT_TAP_CFG_LIR 0 459 460 #define LSM6DSL_REG_TAP_THS_6D 0x59 461 #define LSM6DSL_MASK_TAP_THS_6D_D4D_EN BIT(7) 462 #define LSM6DSL_SHIFT_TAP_THS_6D_D4D_EN 7 463 #define LSM6DSL_MASK_TAP_THS_6D_SIXD_THS (BIT(6) | BIT(5)) 464 #define LSM6DSL_SHIFT_TAP_THS_6D_SIXD_THS 5 465 #define LSM6DSL_MASK_TAP_THS_6D_TAP_THS (BIT(4) | BIT(3) | \ 466 BIT(2) | BIT(1) | \ 467 BIT(0)) 468 #define LSM6DSL_SHIFT_TAP_THS_6D_TAP_THS 0 469 470 #define LSM6DSL_REG_INT_DUR2 0x5A 471 #define LSM6DSL_MASK_INT_DUR2_DUR (BIT(7) | BIT(6) | \ 472 BIT(5) | BIT(4)) 473 #define LSM6DSL_SHIFT_INT_DUR2_DUR 4 474 #define LSM6DSL_MASK_INT_DUR2_QUIET (BIT(3) | BIT(2)) 475 #define LSM6DSL_SHIFT_INT_QUIET 2 476 #define LSM6DSL_MASK_INT_DUR2_SHOCK (BIT(1) | BIT(0)) 477 #define LSM6DSL_SHIFT_INT_SHOCK 0 478 479 #define LSM6DSL_REG_WAKE_UP_THS 0x5B 480 #define LSM6DSL_MASK_WAKE_UP_THS_SINGLE_DOUBLE_TAP BIT(7) 481 #define LSM6DSL_SHIFT_WAKE_UP_THS_SINGLE_DOUBLE_TAP 7 482 #define LSM6DSL_MASK_WAKE_UP_THS_WK_THS (BIT(5) | BIT(4) | \ 483 BIT(3) | BIT(2) | \ 484 BIT(1) | BIT(0)) 485 #define LSM6DSL_SHIFT_WAKE_UP_THS_WK_THS 0 486 487 #define LSM6DSL_REG_WAKE_UP_DUR 0x5C 488 #define LSM6DSL_MASK_WAKE_UP_DUR_FF_DUR5 BIT(7) 489 #define LSM6DSL_SHIFT_WAKE_UP_DUR_FF_DUR5 7 490 #define LSM6DSL_MASK_WAKE_UP_DUR_WAKE_DUR (BIT(6) | BIT(5)) 491 #define LSM6DSL_SHIFT_WAKE_UP_DUAR_WAKE_DUR 5 492 #define LSM6DSL_MASK_WAKE_UP_DUR_TIMER_HR BIT(4) 493 #define LSM6DSL_SHIFT_WAKE_UP_DUR_TIMER_HR 4 494 #define LSM6DSL_MASK_WAKE_UP_DUR_SLEEP_DUR (BIT(3) | BIT(2) | \ 495 BIT(1) | BIT(0)) 496 #define LSM6DSL_SHIFT_WAKE_UP_DUR_SLEEP_DUR 0 497 498 #define LSM6DSL_REG_FREE_FALL 0x5D 499 #define LSM6DSL_MASK_FREE_FALL_DUR (BIT(7) | BIT(6) | \ 500 BIT(5) | BIT(4) | \ 501 BIT(3)) 502 #define LSM6DSL_SHIFT_FREE_FALL_DUR 4 503 #define LSM6DSL_MASK_FREE_FALL_THS (BIT(2) | BIT(1) | \ 504 BIT(0)) 505 #define LSM6DSL_SHIFT_FREE_FALL_THS 0 506 507 #define LSM6DSL_REG_MD1_CFG 0x5E 508 #define LSM6DSL_MASK_MD1_CFG_INT1_INACT_STATE BIT(7) 509 #define LSM6DSL_SHIFT_MD1_CFG_INT1_INACT_STATE 7 510 #define LSM6DSL_MASK_MD1_CFG_INT1_SINGLE_TAP BIT(6) 511 #define LSM6DSL_SHIFT_MD1_CFG_INT1_SINGLE_TAP 6 512 #define LSM6DSL_MASK_MD1_CFG_INT1_WU BIT(5) 513 #define LSM6DSL_SHIFT_MD1_CFG_INT1_WU 5 514 #define LSM6DSL_MASK_MD1_CFG_INT1_FF BIT(4) 515 #define LSM6DSL_SHIFT_MD1_CFG_INT1_FF 4 516 #define LSM6DSL_MASK_MD1_CFG_INT1_DOUBLE_TAP BIT(3) 517 #define LSM6DSL_SHIFT_MD1_CFG_INT1_DOUBLE_TAP 3 518 #define LSM6DSL_MASK_MD1_CFG_INT1_6D BIT(2) 519 #define LSM6DSL_SHIFT_MD1_CFG_INT1_6D 2 520 #define LSM6DSL_MASK_MD1_CFG_INT1_TILT BIT(1) 521 #define LSM6DSL_SHIFT_MD1_CFG_INT1_TILT 1 522 #define LSM6DSL_MASK_MD1_CFG_INT1_TIMER BIT(0) 523 #define LSM6DSL_SHIFT_MD1_CFG_INT1_TIMER 0 524 525 #define LSM6DSL_REG_MD2_CFG 0x5F 526 #define LSM6DSL_MASK_MD2_CFG_INT2_INACT_STATE BIT(7) 527 #define LSM6DSL_SHIFT_MD2_CFG_INT2_INACT_STATE 7 528 #define LSM6DSL_MASK_MD2_CFG_INT2_SINGLE_TAP BIT(6) 529 #define LSM6DSL_SHIFT_MD2_CFG_INT2_SINGLE_TAP 6 530 #define LSM6DSL_MASK_MD2_CFG_INT2_WU BIT(5) 531 #define LSM6DSL_SHIFT_MD2_CFG_INT2_WU 5 532 #define LSM6DSL_MASK_MD2_CFG_INT2_FF BIT(4) 533 #define LSM6DSL_SHIFT_MD2_CFG_INT2_FF 4 534 #define LSM6DSL_MASK_MD2_CFG_INT2_DOUBLE_TAP BIT(3) 535 #define LSM6DSL_SHIFT_MD2_CFG_INT2_DOUBLE_TAP 3 536 #define LSM6DSL_MASK_MD2_CFG_INT2_6D BIT(2) 537 #define LSM6DSL_SHIFT_MD2_CFG_INT2_6D 2 538 #define LSM6DSL_MASK_MD2_CFG_INT2_TILT BIT(1) 539 #define LSM6DSL_SHIFT_MD2_CFG_INT2_TILT 1 540 #define LSM6DSL_MASK_MD2_CFG_INT2_IRON BIT(0) 541 #define LSM6DSL_SHIFT_MD2_CFG_INT2_IRON 0 542 543 #define LSM6DSL_REG_MASTER_CMD_CODE 0x60 544 #define LSM6DSL_REG_SENS_SYNC_SPI_ERROR_CODE 0x61 545 #define LSM6DSL_REG_OUT_MAG_RAW_X_L 0x66 546 #define LSM6DSL_REG_OUT_MAG_RAW_X_H 0x67 547 #define LSM6DSL_REG_OUT_MAG_RAW_Y_L 0x68 548 #define LSM6DSL_REG_OUT_MAG_RAW_Y_H 0x69 549 #define LSM6DSL_REG_OUT_MAG_RAW_Z_L 0x6A 550 #define LSM6DSL_REG_OUT_MAG_RAW_Z_H 0x6B 551 #define LSM6DSL_REG_X_OFS_USR 0x73 552 #define LSM6DSL_REG_Y_OFS_USR 0x74 553 #define LSM6DSL_REG_Z_OFS_USR 0x75 554 555 556 /* Accel sensor sensitivity grain is 0.061 mg/LSB */ 557 #define SENSI_GRAIN_XL (61LL / 1000.0) 558 559 /* Gyro sensor sensitivity grain is 4.375 mdps/LSB */ 560 #define SENSI_GRAIN_G (4375LL / 1000.0) 561 #define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) 562 #define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) 563 #define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) 564 565 #if CONFIG_LSM6DSL_ACCEL_FS == 0 566 #define LSM6DSL_ACCEL_FS_RUNTIME 1 567 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 0 568 #define LSM6DSL_DEFAULT_ACCEL_SENSITIVITY SENSI_GRAIN_XL 569 #elif CONFIG_LSM6DSL_ACCEL_FS == 2 570 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 0 571 #define LSM6DSL_DEFAULT_ACCEL_SENSITIVITY SENSI_GRAIN_XL 572 #elif CONFIG_LSM6DSL_ACCEL_FS == 4 573 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 2 574 #define LSM6DSL_DEFAULT_ACCEL_SENSITIVITY (2.0 * SENSI_GRAIN_XL) 575 #elif CONFIG_LSM6DSL_ACCEL_FS == 8 576 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 3 577 #define LSM6DSL_DEFAULT_ACCEL_SENSITIVITY (4.0 * SENSI_GRAIN_XL) 578 #elif CONFIG_LSM6DSL_ACCEL_FS == 16 579 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 1 580 #define LSM6DSL_DEFAULT_ACCEL_SENSITIVITY (8.0 * SENSI_GRAIN_XL) 581 #endif 582 583 #if (CONFIG_LSM6DSL_ACCEL_ODR == 0) 584 #define LSM6DSL_ACCEL_ODR_RUNTIME 1 585 #endif 586 587 #define GYRO_FULLSCALE_125 4 588 589 #if CONFIG_LSM6DSL_GYRO_FS == 0 590 #define LSM6DSL_GYRO_FS_RUNTIME 1 591 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 4 592 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY SENSI_GRAIN_G 593 #elif CONFIG_LSM6DSL_GYRO_FS == 125 594 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 4 595 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY SENSI_GRAIN_G 596 #elif CONFIG_LSM6DSL_GYRO_FS == 250 597 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 0 598 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY (2.0 * SENSI_GRAIN_G) 599 #elif CONFIG_LSM6DSL_GYRO_FS == 500 600 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 1 601 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY (4.0 * SENSI_GRAIN_G) 602 #elif CONFIG_LSM6DSL_GYRO_FS == 1000 603 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 2 604 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY (8.0 * SENSI_GRAIN_G) 605 #elif CONFIG_LSM6DSL_GYRO_FS == 2000 606 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 3 607 #define LSM6DSL_DEFAULT_GYRO_SENSITIVITY (16.0 * SENSI_GRAIN_G) 608 #endif 609 610 611 #if (CONFIG_LSM6DSL_GYRO_ODR == 0) 612 #define LSM6DSL_GYRO_ODR_RUNTIME 1 613 #endif 614 615 union lsm6dsl_bus_cfg { 616 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 617 struct i2c_dt_spec i2c; 618 #endif 619 620 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 621 struct spi_dt_spec spi; 622 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 623 }; 624 625 struct lsm6dsl_config { 626 int (*bus_init)(const struct device *dev); 627 const union lsm6dsl_bus_cfg bus_cfg; 628 #ifdef CONFIG_LSM6DSL_TRIGGER 629 struct gpio_dt_spec int_gpio; 630 #endif 631 }; 632 633 struct lsm6dsl_data; 634 635 struct lsm6dsl_transfer_function { 636 int (*read_data)(const struct device *dev, uint8_t reg_addr, 637 uint8_t *value, uint8_t len); 638 int (*write_data)(const struct device *dev, uint8_t reg_addr, 639 uint8_t *value, uint8_t len); 640 int (*read_reg)(const struct device *dev, uint8_t reg_addr, 641 uint8_t *value); 642 int (*update_reg)(const struct device *dev, uint8_t reg_addr, 643 uint8_t mask, uint8_t value); 644 }; 645 646 struct lsm6dsl_data { 647 int accel_sample_x; 648 int accel_sample_y; 649 int accel_sample_z; 650 float accel_sensitivity; 651 int gyro_sample_x; 652 int gyro_sample_y; 653 int gyro_sample_z; 654 float gyro_sensitivity; 655 #if defined(CONFIG_LSM6DSL_ENABLE_TEMP) 656 int temp_sample; 657 #endif 658 #if defined(CONFIG_LSM6DSL_EXT0_LIS2MDL) || defined(CONFIG_LSM6DSL_EXT0_LIS3MDL) 659 int magn_sample_x; 660 int magn_sample_y; 661 int magn_sample_z; 662 float magn_sensitivity; 663 #endif 664 #if defined(CONFIG_LSM6DSL_EXT0_LPS22HB) 665 int sample_press; 666 int sample_temp; 667 #endif 668 const struct lsm6dsl_transfer_function *hw_tf; 669 uint16_t accel_freq; 670 671 #ifdef CONFIG_LSM6DSL_TRIGGER 672 const struct device *dev; 673 struct gpio_callback gpio_cb; 674 675 const struct sensor_trigger *data_ready_trigger; 676 sensor_trigger_handler_t data_ready_handler; 677 678 #if defined(CONFIG_LSM6DSL_TRIGGER_OWN_THREAD) 679 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_LSM6DSL_THREAD_STACK_SIZE); 680 struct k_thread thread; 681 struct k_sem gpio_sem; 682 #elif defined(CONFIG_LSM6DSL_TRIGGER_GLOBAL_THREAD) 683 struct k_work work; 684 #endif 685 686 #endif /* CONFIG_LSM6DSL_TRIGGER */ 687 }; 688 689 int lsm6dsl_spi_init(const struct device *dev); 690 int lsm6dsl_i2c_init(const struct device *dev); 691 #if defined(CONFIG_LSM6DSL_SENSORHUB) 692 int lsm6dsl_shub_init_external_chip(const struct device *dev); 693 int lsm6dsl_shub_read_external_chip(const struct device *dev, uint8_t *buf, 694 uint8_t len); 695 #endif 696 697 #ifdef CONFIG_LSM6DSL_TRIGGER 698 int lsm6dsl_trigger_set(const struct device *dev, 699 const struct sensor_trigger *trig, 700 sensor_trigger_handler_t handler); 701 702 int lsm6dsl_init_interrupt(const struct device *dev); 703 #endif 704 705 #endif /* ZEPHYR_DRIVERS_SENSOR_LSM6DSL_LSM6DSL_H_ */ 706
