| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | l4_i2c1_hsi_lptim1_lse.overlay | 76 <&rcc STM32_SRC_HSI I2C1_SEL(2)>,
77 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
|
| D | l4_i2c1_sysclk_lptim1_lsi.overlay | 76 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>,
77 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | f0_i2c1_hsi.overlay | 68 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | f3_i2c1_hsi.overlay | 68 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 69 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | g4_i2c1_hsi_adc1_pllp.overlay | 65 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | g0_i2c1_sysclk_lptim1_lsi.overlay | 69 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
|
| D | wb_i2c1_hsi_lptim1_lse.overlay | 75 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| D | wb_i2c1_sysclk_lptim1_lsi.overlay | 75 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
|
| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 72 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
|
| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 86 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
|
| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/ |
| D | stm32c0_clock.h | 68 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32f0_clock.h | 69 #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) macro
|
| D | stm32l0_clock.h | 71 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32wb_clock.h | 81 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32wl_clock.h | 78 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32wba_clock.h | 80 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) macro
|
| D | stm32f3_clock.h | 72 #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) macro
|
| D | stm32f7_clock.h | 93 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, DCKCFGR2_REG) macro
|
| D | stm32g4_clock.h | 83 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32g0_clock.h | 80 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32l4_clock.h | 82 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) macro
|
| D | stm32u5_clock.h | 92 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) macro
|
| D | stm32h5_clock.h | 126 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR4_REG) macro
|
| /Zephyr-Core-3.5.0/dts/arm/st/f0/ |
| D | stm32f0.dtsi | 191 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
|
