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Searched refs:GIC_CPU_BASE (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dgic.h24 #define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1) macro
140 #define GICC_CTLR (GIC_CPU_BASE + 0x0)
147 #define GICC_PMR (GIC_CPU_BASE + 0x4)
154 #define GICC_BPR (GIC_CPU_BASE + 0x8)
161 #define GICC_IAR (GIC_CPU_BASE + 0xc)
168 #define GICC_EOIR (GIC_CPU_BASE + 0x10)