GICD_ISENABLERn (reference) in projects: Zephyr-Core-3.5.0

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Searched refs:GICD_ISENABLERn (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.5.0/drivers/interrupt_controller/
D	intc_gic.c	`43 sys_write32((1 << int_off), (GICD_ISENABLERn + int_grp * 4)); in arm_gic_irq_enable() 64 enabler = sys_read32(GICD_ISENABLERn + int_grp * 4); in arm_gic_irq_is_enabled() 235 sys_write32(0x0000ffff, GICD_ISENABLERn); in gic_cpu_init()`
/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
D	gic.h	`63 #define GICD_ISENABLERn (GIC_DIST_BASE + 0x100) macro`

TraceRecorderSource-2.7.6
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