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Searched refs:GICD_CTLR (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_gicv3.c65 base = GICD_CTLR; in gic_wait_rwp()
446 sys_write32(0, GICD_CTLR); in gicv3_dist_init()
454 sys_set_bit(GICD_CTLR, GICD_CTRL_NS); in gicv3_dist_init()
455 __ASSERT(sys_test_bit(GICD_CTLR, GICD_CTRL_NS), in gicv3_dist_init()
495 GICD_CTLR); in gicv3_dist_init()
508 GICD_CTLR); in gicv3_dist_init()
511 sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S); in gicv3_dist_init()
Dintc_gic.c170 sys_write32(0, GICD_CTLR); in gic_dist_init()
219 sys_write32(1, GICD_CTLR); in gic_dist_init()
/Zephyr-Core-3.5.0/boards/arm/fvp_baser_aemv8r_aarch32/
Dboard.cmake16 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
/Zephyr-Core-3.5.0/boards/arm64/fvp_baser_aemv8r/
Dboard.cmake16 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dgic.h35 #define GICD_CTLR (GIC_DIST_BASE + 0x0) macro
/Zephyr-Core-3.5.0/boards/arm64/fvp_baser_aemv8r/doc/
Ddebug-with-arm-ds.rst101 …c_ops=1 -C bp.refcounter.non_arch_start_at_default=1 -C gic_distributor.GICD_CTLR-DS-1-means-secur…