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Searched refs:GICC_CTLR_ENABLEGRP0 (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dgic.h176 #define GICC_CTLR_ENABLEGRP0 BIT(0) macro
179 #define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)