Searched refs:FLL (Results 1 – 10 of 10) sorted by relevance
95 int "FLL external reference divider"100 FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
61 | FLL | IMO | 100.0 MHz |
68 The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
94 #define FLL 0x46 macro203 { FLL, 0x00 },
73 with the on-chip FLL to generate a 40 MHz system clock.
83 The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for
103 with the on-chip FLL to generate a 48 MHz system clock.
139 with the on-chip FLL to generate a 40 MHz system clock.
108 The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for
121 The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
